Integrated circuits and methods for forming the integrated circuits
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMing-Chung Liang, Chii-Ping Chen
Life of this patent
Estimating the term…
Abstract
A method for forming an integrated circuit includes forming a first dielectric layer over a gate electrode of a transistor. An etch-stop layer is formed over the first dielectric layer. An opening is formed through the first dielectric layer and the etch-stop layer, exposing a source/drain (S/D) region of the transistor. A metal layer is formed in the opening, contacting the S/D region of the transistor. The metal layer has a surface that is at least partially substantially level with a first top surface of the etch-stop layer. A damascene structure is formed and coupled with the metal layer.
Claims20
A method for forming an integrated circuit, said method comprising:
- forming a first dielectric layer over a gate electrode of a transistor;
- forming an etch-stop layer over the first dielectric layer, the etch-stop layer further has a first top surface and a second top surface, the first top surface is not level with the second top surface;
- forming an opening through the first dielectric layer and the etch-stop layer,
- exposing a source/drain (S/D) region of the transistor;
- forming a metal layer in the opening, contacting the S/D region of the transistor,
- the metal layer having a first surface that extends substantially parallel to an interface between the first dielectric layer and the etch-stop layer and is substantially level with the first top surface of the etch-stop layer, the metal layer is formed at an interface of the first top surface and the second top surface;
- and
- forming a damascene structure coupled with the metal layer.
A method for forming an integrated circuit, said method comprising:
- forming a first dielectric layer over a gate electrode of a transistor;
- forming an etch-stop layer over the first dielectric layer;
- forming a second dielectric layer over the etch-stop layer;
- forming an opening through the second dielectric layer, the etch-stop layer, and the first dielectric layer, exposing a source/drain (S/D) region of the transistor;
- forming a metal material in the opening and over the second dielectric layer;
- removing a portion of the metal material over the second dielectric layer and reducing a thickness of at least a portion of the second dielectric layer in a direction perpendicular to an interface between the first dielectric layer and the etch-stop layer to obtain a metal layer in the opening, the removing has an etch selectivity of the metal material to the etch-stop layer of about 5 or more;
- and
- forming a damascene structure coupled with the metal layer.
A method for forming an integrated circuit, said method comprising:
- forming a first dielectric layer over a gate electrode of a transistor;
- forming an etch-stop layer over the first dielectric layer, the etch-stop layer further has a first top surface and a second top surface, the first top surface is not level with the second top surface;
- forming a second dielectric layer over the etch-stop layer;
- forming an opening through the second dielectric layer, the etch-stop layer, and the first dielectric layer, exposing a source/drain (S/D) region of the transistor;
- forming a metal material in the opening and over the second dielectric layer, the metal layer is formed at an interface of the first top surface and the second top surface;
- removing a portion of the metal material over the second dielectric layer and at least a portion of the second dielectric layer to obtain a metal layer in the opening;
- and
- forming a damascene structure coupled with the metal layer.
Dependencies are inferred from the claim text.