Subtractive patterning to define circuit components
AssigneeNovellus Systems, Inc.
InventorsMichal Danek, Juwen Gao, Ronald A. Powell, Aaron R. Fellis
Life of this patent
Estimating the term…
Abstract
Certain embodiments pertain to local interconnects formed by subtractive patterning of blanket layer of tungsten or other conductive material. The grain sizes of tungsten or other deposited metal can be grown to relatively large dimensions, which results in increased electrical conductivity due to, e.g., reduced electron scattering at grain boundaries as electrons travel from one grain to the next during conduction.
Claims17
A method of preparing vias for a semiconductor device, the method comprising:
- (a) forming a blanket layer of metal over a partially fabricated semiconductor device, wherein the blanket layer has a thickness that is at least about the height of the vias to be prepared;
- (b) providing a pattern of vias on the blanket layer;
- and
- (c) removing regions of the blanket layer to produce the vias defined by the pattern, wherein the vias have grains of the metal, which grains have a size, on average, greater than one-half the width of the smallest via in the pattern.
A method of preparing interconnect lines for a semiconductor device, the method comprising:
- (a) forming a blanket layer of metal over a partially fabricated semiconductor device, wherein the blanket layer has a thickness that is at least about the height of the interconnect lines to be prepared;
- (b) providing a pattern of the interconnect lines on the blanket layer;
- and
- (c) removing regions of the blanket layer to produce the interconnect lines defined by the pattern, wherein the interconnect lines have grains of the metal, which grains have an average size greater than one-half the width of the thinnest interconnect line in the pattern.
Dependencies are inferred from the claim text.