Method of manufacturing semiconductor device and semiconductor device

A method of manufacturing a semiconductor device including a plurality of first field effect transistors in a first region of a semiconductor substrate, a plurality of second field effect transistors in a second region of the semiconductor substrate which is different from the first region, a plurality of third field effect transistors in a third region of the semiconductor substrate which is different from the first region and the second region, first sidewalls each having a first sidewall length and provided over side surfaces of first gate electrodes of the first field effect transistors, second sidewalls each having a second sidewall length and provided over side surfaces of second gate electrodes of the second field effect transistors, and third sidewalls each having a third sidewall length and provided over side surfaces of third gate electrodes of the third field effect transistors, the method comprising the steps of:

• (a) forming the first gate electrodes over a main surface of the semiconductor substrate in the first region each via a first gate insulating film, forming the second gate electrodes over the main surface of the semiconductor substrate in the second region each via a second gate insulating film, and forming the third gate electrodes over the main surface of the semiconductor substrate in the third region each via a third gate insulating film;
• (b) after the step (a), forming a first insulating film over the main surface of the semiconductor substrate so as to cover the first gate electrodes, the second gate electrodes, and the third gate electrodes therewith;
• (c) after the step (b), forming a second insulating film over the first insulating film;
• (d) after the step (c), processing the second insulating film by anisotropic dry etching to leave the second insulating film over each of the side surfaces of the first gate electrodes, the second gate electrodes, and the third gate electrodes;
• (e) after the step (d), processing the second insulating film left over each of the side surfaces of the second gate electrodes and the third gate electrodes by isotropic dry etching or isotropic wet etching;
• (f) after the step (e), processing the first insulating film left over each of the side surfaces of the third gate electrodes by isotropic dry etching or isotropic wet etching;
• and
• (g) after the step (f), removing the exposed first insulating film,
• wherein the first sidewalls are each formed of the first insulating film and the second insulating film which are formed over each of the side surfaces of the first gate electrodes, the second sidewalls are each formed of the first insulating film and the second insulating film which are formed over each of the side surfaces of the second gate electrodes, and the third sidewalls are each formed of the first insulating film and the second insulating film which are formed over each of the side surfaces of the third gate electrodes.

A semiconductor device, comprising:

• a plurality of first field effect transistors in a first region of a semiconductor substrate;
• a plurality of second field effect transistors in a second region of the semiconductor substrate which is different from the first region;
• a plurality of third field effect transistors in a third region of the semiconductor substrate which is different from the first region and the second region;
• first sidewalls each having a first sidewall length and provided over side surfaces of first gate electrodes of the first field effect transistors;
• second sidewalls each having a second sidewall length and provided over side surfaces of second gate electrodes of the second field effect transistors;
• and
• third sidewalls each having a third sidewall length and provided over side surfaces of third gate electrodes of the third field effect transistors,
• wherein the second sidewall length is shorter than the first sidewall length, and the third sidewall length is shorter than the second sidewall length, and
• wherein a height of each of the second sidewalls from a main surface of the semiconductor substrate is shorter than a height of each of the first sidewalls from the main surface of the semiconductor substrate, and a height of each of the third sidewalls from the main surface of the semiconductor substrate is shorter than the height of each of the second sidewalls from the main surface of the semiconductor substrate.