Formation of nitrogen containing dielectric layers having an improved nitrogen distribution

#The present disclosure is directed, in general, to a method for manufacturing gate dielectric layers and, more specifically, to the formation of nitrided gate dielectric layers having an improved nitrogen distribution.

#In certain semiconductor applications it is necessary to integrate dual gate oxide (DGO) thicknesses for associated transistor devices onto a single integrated circuit device. One motivation for performing DGO processing is that high performance transistors typically operate at lower voltages (e.g., 1.5 volts and below), and thus require thinner gate dielectric regions. Alternatively, devices that interface with most conventional external peripherals typically require higher operating voltages (e.g., 1.6 volts and above), and thus require thicker gate dielectric regions. When interfacing lower voltage high performance metal-oxide-semiconductor field-effect-transistors (MOSFETs) within a core of an integrated circuit, to higher voltage peripheral devices, input and output (I/O) buffers of the integrated circuit (IC) are typically designed to contain thicker gate dielectric regions that are compatible with the higher external peripheral device voltages.

#For example, current microcontroller units (MCUs) and digital signal processors (DSPs) are integrating several different types of technology onto a single IC, such as high speed logic, power logic, static random access memory (SRAM), nonvolatile memory (NVM), embedded dynamic random access memory (DRAM), analog circuitry, and other devices and technologies. Many of these devices require different gate dielectric processing and different gate dielectric thicknesses to provide both lower voltage devices within the core of the device and higher voltage devices to interface with external peripheral devices.

#For a more complete understanding of the disclosure, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

#FIG. 1 (Prior Art) illustrates a graph depicting the non-uniformity of nitrogen within a dielectric layer manufactured using conventional techniques;

#FIG. 2 illustrates a semiconductor device manufactured in accordance with the disclosure;

#FIG. 2 illustrates a semiconductor device 200 manufactured in accordance with the disclosure. The device 200 initially includes a semiconductor substrate 210. The substrate 210, in the embodiment of FIG. 2, has isolation structures 215 located therein. The structures 215 may be any isolation structures used in semiconductor devices, including shallow trench isolation structures, field oxide isolation structures, etc.

#As is illustrated in FIG. 2, the structures 215 divide the device 200 into first and second transistor device regions. More particularly in the embodiment of FIG. 2, the structures 215 divide the device 200 into a high voltage device region 220 and a lower voltage device region 250. The term “high voltage device region”, as defined herein, means a device operating at voltages of about 1.6 volts and above. Additionally, the term “lower voltage device region”, as defined herein, means a device operating at voltages of about 1.5 volts and below. Accordingly, the high voltage device region 220 might be configured to provide a low leakage input/output (I/O) device, wherein the lower voltage device region 250 might be configured to provide a high performance core device. It is to be appreciated that the single high and lower voltage device regions 220, 250, are provided for illustrative purposes, and that the device 200 may include a plurality of the high voltage device regions 220 and lower voltage device regions 250 without departing from the disclosure.

#The high voltage device region 220 illustrated in FIG. 2 initially includes a gate structure 230. The gate structure 230 includes a thin nitrogen region 231 located within the substrate 210. The gate structure 230 additionally includes the nitrided gate dielectric layer 233. Because the gate structure 230 forms a part of what will ultimately be a high voltage structure, the gate dielectric layer 233 tends to comprise a thick gate dielectric. For example, the gate dielectric layer 233 in the high voltage device region 220 might have a thickness ranging from about 1.5 nm to about 3.5 nm, or greater. Nevertheless, other thicknesses outside this range could be used.