Vertical transistor with hardening implatation
AssigneeSeagate Technology LLC
InventorsYoung Pil Kim, Hyung-Kew Lee, Peter Nicholas Manos, Chulmin Jung, Maroun Georges Khoury, Dadi Setiadi
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Abstract
A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces.
Claims10
A method comprising:
- providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer, each pillar structure forming a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface;
- implanting an ion species into the vertical pillar transistor top surface;
- oxidizing the vertical pillar transistor forming a top surface oxide material layer and a side surface oxide material layer, wherein the top surface oxide material layer is formed of a different oxide species than the side surface oxide material layer;
- and
- removing selectively the side surface oxide material layer to expose the side surface comprising a rounded side surface and not removing the top surface oxide material layer.
A method comprising:
- providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer, each pillar structure forming a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface, the vertical pillar transistor having a drain, source and channel regions vertically stacked on top of each other and extending away from the semiconductor wafer;
- implanting an ion species into the vertical pillar transistor top surface and not into the vertical pillar transistor side surface;
- oxidizing the vertical pillar transistor forming a top surfaces oxide material layer and a side surface oxide material layer, wherein the top surfaces oxide material layer is formed of a different oxide species than the side surface oxide material layer;
- removing selectively the side surface oxide material layer to expose the side surface comprising a rounded side surface and not removing the top surface oxide material layer;
- and
- electrically coupling a memory cell with the vertical pillar transistor.
Dependencies are inferred from the claim text.