US 8,617,949 B2 · Capacitor and method for making same

Abstract

A system-on-chip device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, and so forth.

Claims20

Dependent claims

A method for forming a system-on-chip (SOC) device comprising:

forming in a common process a first bottom electrode for a first capacitor in a first region, a second bottom electrode for a second capacitor in a second region, and a third bottom electrode for a third capacitor in a third region, wherein the first bottom electrode, the second bottom electrode, and the third bottom electrode are substantially at a same level;
forming a first capacitor insulator with a first thickness adjoining the first bottom electrode, a second capacitor insulator with a second thickness adjoining the second bottom electrode, and a third capacitor insulator with a third thickness adjoining the third bottom electrode;
and
forming in a common process a first top electrode for the first capacitor on the first capacitor insulator, a second top electrode for the second capacitor on the second capacitor insulator, and a third top electrode for the third capacitor on the third capacitor insulator, wherein the first top electrode, the second top electrode, and the third top electrode are substantially at a same level.

1 more element

A method forming a system-on-chip (SOC) device comprising:

forming a first bottom electrode for a first capacitor in a first region, a second bottom electrode for a second capacitor in a second region, and a third bottom electrode for a third capacitor in a third region, wherein the first bottom electrode, the second bottom electrode, and the third bottom electrode are substantially at a same level;
forming in a common process a first sub-layer first capacitor insulator with a first thickness adjoining the first bottom electrode, a first sub-layer second capacitor insulator with the first thickness adjoining the second bottom electrode, and a first sub-layer third capacitor insulator with the first thickness adjoining the third bottom electrode;
removing the first sub-layer third capacitor insulator with the first thickness adjoining the third bottom electrode;
forming in a common process a second sub-layer first capacitor insulator with a second thickness on the first sub-layer first capacitor insulator adjoining the first bottom electrode, a second sub-layer second capacitor insulator with the second thickness on the first sub-layer second capacitor insulator adjoining the second bottom electrode, and a second sub-layer third capacitor insulator with the second thickness adjoining the third bottom electrode;
and
forming a first top electrode for the first capacitor on the second sub-layer first capacitor insulator, a second top electrode for the second capacitor on the second sub-layer second capacitor insulator, and a third top electrode for the third capacitor on the second sub-layer third capacitor insulator, wherein the first top electrode, the second top electrode, and the third top electrode are substantially at a same level.

3 more elements

A method forming a system-on-chip (SOC) device comprising:

forming a first bottom electrode for a first capacitor in a first region, a second bottom electrode for a second capacitor in a second region, and a third bottom electrode for a third capacitor in a third region, wherein the first bottom electrode, the second bottom electrode, and the third bottom electrode are substantially at a same level;
forming in a common process a first sub-layer first capacitor insulator with a first thickness adjoining the first bottom electrode, a first sub-layer second capacitor insulator with the first thickness adjoining the second bottom electrode, and a first sub-layer third capacitor insulator with the first thickness adjoining the third bottom electrode;
removing the first sub-layer second capacitor insulator with the first thickness adjoining the second bottom electrode;
forming in a common process a second sub-layer first capacitor insulator with a second thickness on the first sub-layer first capacitor insulator adjoining the first bottom electrode, a second sub-layer second capacitor insulator with the second thickness adjoining the second bottom electrode, and a second sub-layer third capacitor insulator with the second thickness on the first sub-layer third capacitor insulator adjoining the third bottom electrode, wherein the first thickness is different from the second thickness;
and
forming a first top electrode for the first capacitor on the second sub-layer first capacitor insulator, a second top electrode for the second capacitor on the second sub-layer second capacitor insulator, and a third top electrode for the third capacitor on the second sub-layer third capacitor insulator, wherein the first top electrode, the second top electrode, and the third top electrode are substantially at a same level.

3 more elements

Dependencies are inferred from the claim text.

Capacitor and method for making same

Life of this patent

Capacitor and method for making same

Life of this patent

Abstract

Claims20