Back side alignment structure and manufacturing method for three-dimensional semiconductor device packages

A method for packaging integrated circuit die, the method comprising:

• forming a panel comprising
• one or more integrated circuit die,
• a plurality of alignment die, wherein
• the alignment die comprise fiducial markings on a major surface of the alignment die, and
• the panel has first and second major surfaces;
• encapsulating the one or more integrated circuit die in the panel with an active surface of each integrated circuit die being exposed at the first major surface of the panel;
• and
• encapsulating the plurality of alignment die in the panel with the major surface of the alignment die being exposed at the second major surface of the panel, wherein
• the fiducial markings are exposed at the second major surface of the panel, and
• said encapsulating the integrated circuit die and the plurality of alignment die is performed using an encapsulant.