On-Chip RF shields with front side redistribution lines
AssigneeInfineon Technologies AG
InventorsHans-Joachim Barth, Thorsten Meyer, Markus Brunnbauer, Jenei Snezana
Life of this patent
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Abstract
A system on chip comprising a RF shield is disclosed. In one embodiment, the system on chip includes a RF component disposed on a chip, first redistribution lines disposed above the system on chip, the first redistribution lines coupled to I/O connection nodes. The system on chip further includes second redistribution lines disposed above the RF component, the second redistribution lines coupled to ground potential nodes. The second redistribution lines include a first set of parallel metal lines coupled together by a second set of parallel metal lines.
Claims20
A method of fabricating a system on a chip, the method comprising:
- forming a radio frequency (RF) device in a first region of a substrate and forming a semiconductor device in a second region of the substrate, the first region and second region separated by a third region comprising no active devices;
- forming a stack of metal lines and vias disposed on the third region;
- forming a pad disposed on a last metal line of the stack of metal lines and vias;
- and
- forming redistribution lines over the last metal line and coupled to the pad, wherein the redistribution lines are coupled to a ground potential node and form a first structure above the first region, the first structure comprises a structure selected from the group consisting of a mesh, a finger, a plate, or a combination thereof.
A method of fabricating a semiconductor chip, the method comprising:
- dicing a wafer to form individual chips;
- arranging the individual chips on an adhesive tape, the individual chips being separated by a gap of a predetermined distance;
- filling the gap between the individual chips with a mold compound;
- curing the mold compound and separating from the adhesive tape to form a reconfigured wafer;
- and
- forming first redistribution lines on the reconfigured wafer, wherein the first redistribution lines are coupled together and to a ground potential node, wherein the first redistribution lines are arranged to form a first set of parallel metal lines, the first set of parallel metal lines being coupled together by a second set of parallel metal lines.
A method of fabricating a semiconductor chip, the method comprising:
- providing a plurality of semiconductor chips, each chip including a substrate comprising a radio frequency (RF) device in a first region of the substrate and a semiconductor device in a second region of the substrate, the first region and second region separated by a third region comprising no active devices, wherein through substrate vias are disposed in the third region;
- forming a reconfigured wafer from the plurality of semiconductor chips by arranging the plurality of semiconductor chips next to each other and filling a gap between adjacent chips of the plurality of semiconductor chips with a molding compound, the reconfigured wafer comprising the molding compound surrounding each chip of the plurality of semiconductor chips;
- forming through vias in the molding compound;
- and
- coupling the through substrate vias and the through vias to a node coupled to a ground potential.
Dependencies are inferred from the claim text.