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US 8,610,464 B2Granted
Low-current inverter circuit
AssigneeEpcos AG
InventorErwin Spits
Life of this patent
Estimating the term…
Abstract
The circuit includes an E-mode transistor with gate-source junction, a D-mode transistor with gate-source junction, a component generating a voltage drop between the source of the D-mode transistor and the drain of the E-mode transistor, and a connection between the drain of the E-mode transistor and the gate of the D-mode transistor. The gate of the E-mode transistor is provided for an input signal, and the drain of the E-mode transistor is provided for an output signal.
Claims16
An inverter circuit, comprising:
- an input transistor and a feedback transistor, each comprising a source, a drain and a gate that is provided to control a channel between the source and the drain, and each having a gate-source junction,
- wherein the input transistor conducts between the source and the drain if a gate-source voltage that is applied between the gate and the source is more positive than a positive threshold voltage, and does not conduct between the source and the drain otherwise,
- wherein the feedback transistor does not conduct between the source and the drain if a gate-source voltage that is applied between the gate and the source is more negative than a negative threshold voltage, and conducts between the source and the drain otherwise,
- a component that generates a voltage drop between the source of the feedback transistor and the drain of the input transistor,
- a connection between the drain of the input transistor and the gate of the feedback transistor,
- wherein the source of the input transistor is to be connected to a first voltage level of a supply voltage,
- wherein the drain of the feedback transistor is to be connected to a second voltage level of the supply voltage,
- wherein the gate of the input transistor is provided for an input signal,
- wherein the drain of the input transistor is provided for an output signal,
- a buffer circuit forming an output stage, wherein the buffer circuit comprises an inverter circuit comprising:
- a second input transistor and a second feedback transistor, each comprising a source, a drain and a gate that is provided to control a channel between the source and the drain, and each having a second gate-source junction,
- wherein the second input transistor conducts between the source and the drain if a gate-source voltage that is applied between the gate and the source is more positive than a positive threshold voltage, and does not conduct between the source and the drain otherwise,
- wherein the second feedback transistor does not conduct between the source and the drain if a gate-source voltage that is applied between the gate and the source is more negative than a negative threshold voltage, and conducts between the source and the drain otherwise,
- a second component that generates a voltage drop between the source of the second feedback transistor and the drain of the second input transistor,
- a second connection between the drain of the second input transistor and the gate of the second feedback transistor,
- wherein the source of the second input transistor is to be connected to a first voltage level of the supply voltage,
- wherein the drain of the second feedback transistor is to be connected to a second voltage level of the supply voltage,
- wherein the gate of the second input transistor is provided for a second input signal, and
- wherein the drain of the second input transistor is provided for a second output signal.
16 more elements
A circuit comprising:
- an enhancement mode junction field effect transistor (JFET) with a gate-source junction;
- a depletion mode JFET with a gate-source junction;
- a component generating a voltage drop between a source of the depletion mode JFET and a drain of the enhancement mode JFET;
- and
- a connection between the drain of the enhancement mode JFET and a gate of the depletion mode JFET;
- wherein the component comprises first and second further enhancement mode transistors, a gate of the first further enhancement mode transistor being coupled to the source of the depletion mode JFET, a gate of the second further enhancement mode transistor being coupled to a source of the first further enhancement mode transistor, and a source of the second further enhancement mode transistor being coupled to the drain of the enhancement mode JFET.
3 more elements
Dependencies are inferred from the claim text.