Memory access to a dual in-line memory module form factor flash memory

An apparatus for memory access to a dual in-line memory module (DIMM) form factor flash memory, the apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that when executed cause the apparatus to:

• receive, by a controller from a processor through cacheable memory in the processor, a read request;
• transmit, by the controller, the read request to the DIMM form factor flash memory;
• poll, by the controller, a read queue in the DIMM form factor flash memory until data is ready for the read request;
• copy from the DIMM form factor flash memory, by the controller, the data corresponding to the read request to a read queue in the controller;
• transmit, by the controller on an interface between the controller and the processor, an invalidate command for the cacheable memory;
• and
• in response to receiving the invalidate command, read by the processor the data stored in the read queue in the controller.

A computer program product for memory access to a dual in-line memory module (DIMM) form factor flash memory, the computer program product disposed upon a computer readable storage medium, the computer program product comprising computer program instructions capable, when executed, of causing a computer to carry out the steps of:

• receiving, by a controller from a processor through cacheable memory in the processor, a read request;
• transmitting, by the controller, the read request to the DIMM form factor flash memory;
• polling, by the controller, a read queue in the DIMM form factor flash memory until data is ready for the read request;
• copying from the DIMM form factor flash memory, by the controller, the data corresponding to the read request to a read queue in the controller;
• transmitting, by the controller on an interface between the controller and the processor, an invalidate command for the cacheable memory;
• and
• in response to receiving the invalidate command, reading by the processor the data stored in the read queue in the controller.