Nonvolatile semiconductor memory
AssigneeKabushiki Kaisha Toshiba
InventorsNaofumi Abiko, Masahiro Yoshihara
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a nonvolatile semiconductor memory includes a memory cell array including memory cells of a first unit in which read and write are parallelly performed, n (n is a natural number of not less than 2) sense amplifiers, n detection circuits corresponding to the n sense amplifiers, an accumulator configured to divide the first unit data read from the memory cell array into z (z is a natural number) second unit data and accumulate a fail bit for which the write is incomplete for the second unit data, and a control circuit configured to control an operation of detecting the fail bit after the write.
Claims20
A nonvolatile semiconductor memory comprising:
- a memory cell array including memory cells of a first unit in which read and write are parallelly performed;
- n (n is a natural number of not less than 2) sense amplifiers;
- n detection circuits corresponding to the n sense amplifiers;
- an accumulator configured to divide the first unit data read from the memory cell array into z (z is a natural number) second unit data and accumulate a fail bit for which the write is incomplete for the second unit data;
- and
- a control circuit configured to control an operation of detecting the fail bit after the write,
- wherein the control circuit
- stores third unit data of each second unit data in one of the n sense amplifiers,
- reads one bit of each second unit data from one of the n sense amplifiers so as to parallelly read a total of z bits,
- detects the fail bit from the z bits using one of the n detection circuits, and
- transfers the z bits to the accumulator so as to accumulate the fail bits for each second unit data.
A nonvolatile semiconductor memory comprising:
- a memory cell array including memory cells of a first unit in which read and write are parallelly performed;
- n (n is a natural number of not less than 2) sense amplifiers;
- n detection circuits corresponding to the n sense amplifiers;
- an accumulator configured to divide the first unit data read from the memory cell array into z (z is a natural number) second unit data and accumulate a fail byte for which the write is incomplete for the second unit data;
- and
- a control circuit configured to control an operation of detecting the fail byte after the write,
- wherein the control circuit
- stores third unit data of each second unit data in one of the n sense amplifiers,
- reads one bit from one of the n sense amplifiers by wired OR-connecting one byte of each second unit data so as to parallelly read a total of z bits,
- detects the fail byte from the z bits using one of the n detection circuits, and
- transfers the z bits to the accumulator so as to accumulate the fail bytes for each second unit data.
Dependencies are inferred from the claim text.