Sea-of-fins structure on a semiconductor substrate and method of fabrication
AssigneeInternational Business Machines Corporation
InventorsHoward H. Chen, Louis C. Hsu, Jack A. Mandelman, Chun-Yung Sung
Life of this patent
Estimating the term…
Abstract
A semiconductor device and a method of fabricating a semiconductor device, wherein the method includes forming, on a substrate, a plurality of planarized fin bodies to be used for customized fin field effect transistor (FinFET) device formation; forming a nitride spacer around each of the plurality of fin bodies; forming an isolation region in between each of the fin bodies; and coating the plurality of fin bodies, the nitride spacers, and the isolation regions with a protective film. The fabricated semiconductor device is adapted to be used in customized applications as a customized semiconductor device.
Claims18
A semiconductor device used in customized applications as a customized semiconductor device, comprising:
- a silicon (Si) substrate having a transverse x-axis and a longitudinal y-axis;
- a plurality of parallel oxide isolation regions oriented longitudinally on said Si substrate, each of said plurality of parallel oxide isolation regions being separated one from the other by an equal distance and having an equal height;
- a plurality of parallel Si fin bodies oriented longitudinally on Si said substrate customized to comprise at least one fin of a fin field effect transistor (FinFET) and at least one electrode of a capacitor, each of said plurality of parallel Si fin bodies interposed midway between adjacent parallel oxide isolation regions, having an equal width and an equal height less than said equal height of said plurality of parallel oxide isolation regions;
- a dielectric formed on a top surface and lateral surfaces of each of said plurality of parallel Si fin bodies;
- and
- a polysilicon layer formed on a longitudinal portion of said top surface and said lateral surfaces corresponding to said longitudinal portion of each of said plurality of parallel Si fin bodies to said Si substrate, a top surface of said polysilicon layer being coplanar with a top surface of said plurality of parallel oxide isolation regions,
- said polysilicon layer forming a gate of said FinFET, when formed on said at least one fin of said FinFET, and
- said polysilicon layer forming a top electrode of said capacitor, when formed on said at least one electrode of said capacitor.
A semiconductor device used in customized applications as a customized semiconductor device comprising:
- a substrate;
- a plurality of planarized fin bodies on said substrate, wherein said plurality of planarized fin bodies are used for customized fin field effect transistor (FinFET) device formation;
- nitride spacers around each of said plurality of planarized fin bodies;
- isolation regions in between each of said plurality of planarized fin bodies;
- a protective film on said plurality of planarized fin bodies, said nitride spacers, and said isolation regions;
- said nitride spacers being selectively removed from selected areas of said semiconductor device formed into source/drain regions of said FinFET;
- and
- said semiconductor device further comprises an epitaxial material in said selected areas.
A customized semiconductor device, comprising:
- a silicon (Si) substrate having a transverse x-axis and a longitudinal y-axis;
- a plurality of parallel oxide isolation regions oriented longitudinally on said Si substrate, each of said plurality of parallel oxide isolation regions being separated one from the other by an equal distance of 120 nm, and having an equal height;
- a plurality of parallel Si fin body bodies oriented longitudinally on said Si substrate, customized to comprise at least one fin of a fin field effect transistor (FinFET) and at least one electrode of a capacitor, each of said plurality of parallel Si fin bodies interposed midway between adjacent parallel oxide isolation regions, having an equal width of 40 nm, and having an equal height less than said equal height of said parallel oxide isolation regions;
- a dielectric formed on a top surface and lateral surfaces of each of said plurality of parallel Si fin bodies;
- and
- a polysilicon layer formed on a longitudinal portion of said top surface and said lateral surfaces corresponding to said longitudinal portion of each of said plurality of parallel Si fin bodies to said Si substrate, a top surface of said polysilicon layer being coplanar with a top surface of said plurality of parallel oxide isolation regions,
- said polysilicon layer forming a gate of said FinFET, when formed on said at least one fin of said FinFET, and
- said polysilicon layer forming a top electrode of said capacitor, when formed on said at least one electrode of said capacitor.
Dependencies are inferred from the claim text.