Structure and method for forming conductive path in resistive random-access memory device

A method for forming a resistive random-access memory (RRAM) device, said method comprising:

• providing a plurality of bit cells, each including a transistor and resistive element, said bit cells arranged in vertical columns, each said bit cell having said transistor having one source/drain coupled to a vertical bit line and the other source/drain coupled to a first terminal of said resistive element;
• providing a plurality of word lines coupled to respective gates of said transistors and arranged in a horizontal direction;
• providing a plurality of source lines arranged in said horizontal direction and each coupled to an opposed terminal of at least one of said resistive elements;
• and
• forming conductive paths in said resistive elements of two adjacent bit cells of said plurality of bit cells, disposed along a first vertical bit line at least by biasing a first source line of said source lines to produce a sufficiently high voltage across each said associated resistive elements.

A method for forming a resistive random-access memory (RRAM) device, said method comprising:

• providing a plurality of bit cells, each including a transistor and resistive element, said bit cells arranged in vertical columns, each said bit cell having said transistor having one source/drain coupled to a vertical bit line of a plurality of vertical bit lines and the other source/drain coupled to a first terminal of said resistive element;
• providing a plurality of word lines coupled to respective gates of said transistors and arranged in a horizontal direction;
• providing a plurality of source lines arranged in said horizontal direction and including a first source line coupled to opposed ends of adjacent resistive elements of said resistive elements in adjacent bit cells of said plurality of bit cells disposed along a first vertical bit line and further coupled to opposed ends of further adjacent resistive elements of said resistive elements in further adjacent bit cells of said plurality of bit cells disposed along a second vertical bit line of said plurality of vertical bit lines;
• biasing said first source line to apply a forming voltage to a terminal of each of said adjacent resistive elements and each of said further adjacent resistive elements;
• and
• forming conductive paths in said adjacent resistive elements but not in said further adjacent resistive elements by applying a voltage greater than a threshold voltage to two word lines of said plurality of word lines coupled to gates of said transistors in said adjacent bit cells and said further adjacent bit cells.