Digital video data relay

A video data transmission link, comprising:

• an input channel adapted to receive input video data packets from a single input video data stream having one or more input lanes and associated with a stream clock signal having a first period;
• a first circuit configured to:
• generate a local clock signal having a second time period;
• convert the input video data packets into data for a display device;
• and
• transmit, in a link signal, the data for the display device and a factor relating the first period to the second period;
• a second circuit coupled to the first circuit and configured to:
• receive the link signal from the first circuit;
• obtain the factor from the link signal;
• recover, based on the factor and the second period, the stream clock signal;
• retime and recondition the converted data using the stream clock signal;
• and
• an output channel configured to:
• receive the video data packets in an output format from the second circuit;
• and
• provide the video data packets into a single output video data stream having one or more output lanes, wherein the number of output lanes is different than the number of input lanes.

A daisy chain of video display devices, comprising:

• a source of digital video data;
• a plurality of video display devices wherein a first video display device is coupled to the source of the video data, and each further video display device receives the sources video signal from the previous display device and provides the source video signal to the next video display device;
• further wherein at least one of the video display devices comprises a video relay circuit further comprising:
• an input channel adapted to receive input video data packets from an input video data stream, wherein the input video data stream is in High Definition Multimedia Interface (HDMI) format associated with a stream clock signal having a first period;
• a first circuit configured to:
• generate a local clock signal having a second period;
• convert the input video data packets into DisplayPort (DP) video data packets for a display device;
• and
• transmit, in a link signal, the DP video data packets and a factor relating the first period to the second period;
• a second circuit coupled to the first circuit and configured to:
• receive the link signal from the first circuit;
• obtain the factor from the link signal;
• recover, based on the factor and the second period, the stream clock signal;
• and
• retime and recondition the DP video data packets using the stream clock signal;
• and
• an output channel adapted to receive the DP video data packets from the second circuit, and to provide the DP video data packets into an output video data stream, wherein the output video data stream is in HDMI format.