ASIP architecture for executing at least two decoding methods

A computer based automated method of exploring decoding methods and an instruction set suitable therefor to allow selection for each of the decoding methods one approximation and a corresponding instruction set, changed codes of each of the decoding methods by a plurality of fixed point approximations making use of the instruction sets being available, the method comprising:

• loading at least two decoding methods;
• loading a template of an application specific instruction set processor (ASIP) device with a plurality of possible instruction sets;
• and
• computing the performance of the execution of each of the approximations on the device, the corresponding instruction set being the same for the at least two decoding methods,
• wherein the method is performed by a computer.

A system for executing a decoding method, the system being capable of executing at least two data decoding methods which are different in underlying coding principle, wherein at least one of the data decoding methods requires data shuffling operations on the data, the system comprising:

• at least one application specific instruction set processor (ASIP) core having an instruction set comprising arithmetic operators excluding multiplication, division and power, the ASIP core configured to execute approximations of each of the at least two data decoding methods;
• at least a first memory unit configured to store data;
• a transfer unit configured to transfer data from the first memory unit towards the at least one ASIP core, the transfer unit comprising a data shuffler;
• and
• a controller configured to control the data shuffler independent from the ASIP core.

A method of decoding data using a programmable ASIP core and a memory structure, comprising:

• loading an approximation of a decoding method onto a programmable application specific instruction set processor (ASIP) core;
• loading coded data;
• and
• decoding the data by the approximation, wherein decoding the data comprises executing arithmetic operations on the coded data by the programmable ASIP core and controlling scheduling of data accesses to a memory structure by a controller separate form the ASIP core, wherein controlling scheduling of data accesses comprises controlling data shuffling from the memory structure by a controller separate from the ASIP core.

A system for executing a decoding method, the system being capable of executing at least two data decoding methods which are different in underlying coding principle, wherein at least one of the data decoding methods requires data shuffling operations on the data, the system comprising:

• means for executing approximations of each of the at least two data decoding methods, the executing means comprising an instruction set comprising arithmetic operators excluding multiplication, division and power;
• means for storing data;
• means for transferring data from the storing means towards the executing means, the transferring means comprising a data shuffler;
• and
• means for controlling the data shuffler independent from the executing means.