US 8,577,952 B2 · Combined binary/decimal fixed-point multiplier and method

Abstract

A combined binary/decimal fixed-point multiplier that uses BCD-4221 recoding for the decimal digits. This allows the use of binary carry-save hardware to perform decimal addition with a small correction. The described designs provide an improved reduction tree organization to reduce the area and delay of the multiplier and improved reduction tree components that leverage the redundant decimal encodings to help reduce delay. A split reduction tree architecture is also introduced that reduces the delay of the binary product with only a small increase in total area. Area and delay estimates are presented that show that the proposed designs have significant area improvements over separate binary and decimal multipliers while still maintaining similar latencies for both decimal and binary operations.

Claims10

Dependent claims

A combined binary decimal multiplier comprising:

a plurality of binary multiple generators configured to receive a first input and to generate a first output based on the first input;
a plurality of binary recording elements configured to receive a second input and to generate a second output;
based on the second input;
a partial product selector having an binary decimal doubling unit configured to receive the first output and the second output and to generate a third output;
a split 33:2 partial product reduction tree configured to receive the third output and to generate a binary output and a decimal output, the split 33:2 partial product reduction tree comprising a plurality of 3:2 carry save adders;
and
a 128 bit combined binary/decimal conditional quaternary tree adder configured to perform carry-propagate addition of the binary output and the decimal output.

4 more elements

Dependencies are inferred from the claim text.

Combined binary/decimal fixed-point multiplier and method

Life of this patent

Combined binary/decimal fixed-point multiplier and method

Life of this patent

Abstract

Claims10