Methods and apparatus in alternate finite field based coders and decoders

An apparatus for encoding a first sequence of n-state symbols, each n-state symbol being represented by a signal, comprising:

• an input of a device enabled to receive the first sequence of n-state symbols;
• the device enabled for processing the first plurality of n-state symbols by implementing a single truth table that is a truth table of a modified addition over an alternate finite field GF(n), wherein the alternate finite field GF(n) is a finite field defined by the addition, a multiplication and a neutral element of the addition;
• wherein the neutral element of the addition is not 0 and the modified addition over the alternate finite field GF(n) is the addition over the alternate finite field GF(n) that is modified by at least one n-state inverter defined by the multiplication over the alternate finite field GF(n) wherein n is an integer greater than 4;
• and wherein
• the apparatus is part of a communication system or a data storage system;
• and an output that provides a second sequence of symbols as a result of the processing.

A method for decoding a sequence of encoded n-state symbols with n>4, each n-state symbol in the sequence of encoded n-state symbols being represented by a signal, comprising:

• providing a plurality of signals representing the encoded sequence of n-state symbols to an input of a processor;
• wherein
• the encoded sequence of n-state symbols was generated using an encoder in the group consisting of a convolutional encoder, a Reed-Solomon encoder, a Hamming coder, a check-symbol based error correcting encoder, a transposition encoder, a hopping rule encoder, a streaming cipher encoder, a block coder, a Feistel-like network based encodes an Elliptic Curve Coding encoder, a symbol statistical distribution modifying encoder, a Galois Field arithmetic based encoder and an Advanced Encryption Standard (AES) encoder;
• the processor processing the plurality of signals representing the encoded sequence of n-state symbols by an implementation of an addition and a multiplication over an alternate finite field, wherein the addition and the multiplication over the alternate finite field define the alternate finite field;
• wherein a zero element of the alternate finite field is a neutral element of the addition over the alternate finite field and is not 0;
• and an output providing a plurality of signals representing a decoded sequence of n-state symbols on an output as a result of the processing.