Concealing plain text in scrambled blocks
AssigneeViXS Systems, Inc.
InventorsPaul D. Ducharme, Weiguo Jao
Life of this patent
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Abstract
An apparatus generally having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) divide a plain text into at least three input blocks and (ii) generate at least three scrambled blocks by scrambling the input blocks using a first cipher process. The first cipher process may be configured such that a first of the input blocks does not affect the generation of a last scrambled block. The second circuit may be configured to (i) generate at least three output blocks by de-scrambling the scrambled blocks using a second cipher process and (ii) reconstruct the plain text from the output blocks. The second cipher process may be configured such that a first of the scrambled blocks affects the generation of all of the output blocks.
Claims19
An apparatus comprising:
- a first circuit configured to (i) divide a plain text into at least three input blocks and (ii) generate at least three scrambled blocks by scrambling said input blocks using a first cipher process, said first cipher process being configured such that a first of said input blocks does not affect said generation of a last of said scrambled blocks;
- and
- a second circuit configured to (i) generate at least three output blocks by de-scrambling said scrambled blocks using a second cipher process and (ii) reconstruct said plain text from said output blocks, said second cipher process being configured such that the plain text from a first of said scrambled blocks is arithmetically combined with at least one other of said output blocks in de-scrambling the at least one other of said output blocks.
A method for concealing plain text in scrambled blocks, comprising the steps of:
- (A) dividing said plain text into at least three input blocks via a pre-processor;
- (B) generating via a scrambler, at least three of said scrambled blocks by scrambling said input blocks using a first cipher process in a first circuit, said first cipher process being configured such that a first of said input blocks does not affect said generation of a last of said scrambled blocks;
- (C) generating, via a descrambler, at least three output blocks by de-scrambling said scrambled blocks using a second cipher process in a second circuit, said second cipher process being configured such that the plain text from a first of said scrambled blocks is arithmetically combined with at least one other of said output blocks in de-scrambling the at least one other of said output blocks;
- and
- (D) reconstructing said plain text from said output blocks via a post processor.
Dependencies are inferred from the claim text.