Phase-locked loop

A phase-locked loop circuit for generating a pixel-clock signal based on a horizontal synchronization signal, comprising:

• a phase-frequency detector having an input to receive the horizontal synchronization signal and a frequency divided pixel-clock signal, and arranged to generate up and down signals based on the horizontal synchronization signal and the frequency-divided pixel-clock signal;
• a charge pump having an input to receive the up and down signals from the phase-frequency detector, and arranged to generate an output signal based on the up and down signals;
• a loop filter having an input to receive the output signal from the charge pump, and arranged to generate a frequency-control signal based on the output signal of the charge pump;
• a voltage-controlled oscillator having an input to receive the frequency-control signal from the loop filter, and arranged to generate an oscillating signal and adjust a frequency of the oscillating signal in response to the frequency-control signal, wherein the voltage-controlled oscillator is adapted to have a tuning range with a center frequency which is larger than or equal to 4 GHz;
• a programmable first frequency divider having an input to receive the oscillating signal from the voltage-controlled oscillator, and arranged to generate the pixel-clock signal by frequency division of the oscillating signal;
• and
• a programmable second frequency divider having an input to receive the pixel-clock signal from the programmable first frequency divider, and arranged to generate the frequency divided pixel-clock signal by frequency division of the pixel-clock signal.