Configurable all-digital coherent demodulator system for spread spectrum applications

A configurable demodulator for demodulating a user code from a received signal, the configurable demodulator comprising:

• a first multiply-logic device configured to multiply a first product code with an encoded data signal to produce a first code demodulated chip sequence, the first product code including at least a user code sequence;
• a first accumulator coupled to the first multiply-logic device, the first accumulator configured to sum the first code demodulated chip sequence to produce a first code-demodulated sample;
• a second multiply-logic device configured to multiply a second product code with the encoded data signal to produce a second code demodulated chip sequence, the second product code including at least a user code sequence;
• a second accumulator coupled to the second multiply-logic device, the second accumulator configured to sum the second code demodulated chip sequence to produce a second code-demodulated sample;
• and
• a compare circuit coupled to the first accumulator and the second accumulator, the compare circuit configured to compare a desired integration length to a current integration length, and configured to provide a dump enable signal to the first accumulator and the second accumulator.

A configurable demodulator for demodulating a user code from a received signal, the configurable demodulator comprising:

• a first multiply-logic device configured to multiply a first product code with an encoded data signal to produce a first code demodulated chip sequence, the first product code including at least a user code sequence;
• a first accumulator coupled to the first multiply-logic device, the first accumulator configured to sum the first code demodulated chip sequence to produce a first code-demodulated sample;
• a second multiply-logic device configured to multiply a second product code with the encoded data signal to produce a second code demodulated chip sequence, the second product code including at least a user code sequence;
• and
• a second accumulator coupled to the second multiply-logic device, the second accumulator configured to sum the second code demodulated chip sequence to produce a second code-demodulated sample,
• wherein the first accumulator and the second accumulator each have separate add-logic devices for adding an in-phase portion and a quadrature-phase of a signal.

A configurable demodulator for demodulating a traffic channel from a received signal, the configurable demodulator comprising:

• a first multiplier configured to multiply a traffic code sequence with a first received demodulated sample of the received signal to produce a first demodulated data sequence;
• a first accumulator coupled to the first multiplier, the first accumulator configured to sum the first demodulated data sequence to produce a first intermediate demodulated output data sample;
• a second multiplier configured to multiply the traffic code sequence with a second intermediate code demodulated sequence to produce a second intermediate code demodulated sequence;
• a second accumulator coupled to the second multiplier, the second accumulator configured to sum the second intermediate code demodulated sequence to produce the second demodulated output data sample;
• and
• a first adder coupled to the first accumulator and the second accumulator, the first adder configured to add an in-phase component from the first accumulator to a quadrature-phase component from the second accumulator.

A method of demodulating a user code from a received signal using a configurable user-code demodulator, the method comprising:

• a) receiving a channel signal at an extended code/long code demodulator;
• b) multiplying a first product code with an encoded data signal at a first multiply-logic device to produce a first code demodulated chip sequence;
• c) summing the first code demodulated chip sequence at a first accumulator to produce a first code-demodulated sample;
• d) multiplying a second product code with the encoded data signal at a second multiply-logic device to produce a second code demodulated chip sequence;
• and
• e) summing the second code demodulated chip sequence at a second accumulator to produce a second code demodulated sample,
• wherein adding steps c) and e) comprise:
• adding a first m-ary component of a signal at a first adder component;
• and
• adding a second m-ary component of a signal at a second adder component.

A method of demodulating a user code from a received signal using a configurable user-code demodulator, the method comprising:

• a) receiving a channel signal at an extended code/long code demodulator;
• b) multiplying a first product code with an encoded data signal at a first multiply-logic device to produce a first code demodulated chip sequence;
• c) summing the first code demodulated chip sequence at a first accumulator to produce a first code-demodulated sample;
• d) multiplying a second product code with the encoded data signal at a second multiply-logic device to produce a second code demodulated chip sequence;
• e) summing the second code demodulated chip sequence at a second accumulator to produce a second code demodulated sample;
• h)f) receiving a desired integration length value;
• i)g) comparing the desired integration length value to a current integration length at a compare circuit;
• and
• j)h) providing a dump enable signal to the first accumulator and the second accumulator if the current integration length satisfies the desired integration length.

A method of demodulating a traffic channel from a received signal at a configurable traffic channel demodulator, the method comprising:

• a) receiving a first code demodulated sample and a second code demodulated sample;
• b) receiving a traffic code sequence;
• c) multiplying the traffic code sequence with the first code demodulated sample at a first multiplier to produce a first demodulated data sequence;
• d) summing the first demodulated data sequence at a first accumulator to produce a first intermediate output data sample;
• e) multiplying the traffic code with the second code demodulated sample at a second multiplier to produce a second demodulated data sequence;
• f) summing the second demodulated data sequence at a second accumulator to produce a second intermediate output data sample;
• g) adding an in-phase component of the first intermediate output data sample to a quadrature-phase component of the second intermediate output data sample at a first adder to obtain the quadrature-phase demodulated output data sample;
• and
• h) subtracting the in-phase component of the second intermediate output data sample from a quadrature-phase component of the first intermediate output data sample at a second adder to obtain an in-phase demodulated output data sample.

A configurable digital coherent demodulator system for demodulating a digital signal, the digital coherent configurable demodulator system comprising:

• a user code demodulator configured to demodulate a user code from a received signal, the user code demodulator comprising:
• a first multiplier device configured to multiply a first product code with an encoded data signal to produce a first code demodulated chip sequence, the first product code including at least a user code sequence;
• a first accumulator coupled to the first multiplier, the first accumulator configured to sum the first code demodulated chip sequence to produce a first code-demodulated sample;
• a second multiplier configured to multiply a second product code with the encoded data signal to produce a second code demodulated chip sequence, the second product code including at least a user code sequence;
• and
• a second accumulator coupled to the second multiplier, the second accumulator configured to sum the second code demodulated chip sequence to produce a second code-demodulated sample;
• and
• a traffic channel demodulator coupled to the user code demodulator, the traffic channel demodulator configured to demodulate a traffic channel from the received signal, the traffic channel demodulator comprising:
• a third multiplier configured to multiply a traffic code sequence with the first code-demodulated sample to produce a first demodulated data sequence;
• a third accumulator coupled to the third multiplier, the third accumulator configured to sum the first demodulated data sequence to produce a first intermediate output data sample;
• a fourth multiplier configured to multiply the traffic code sequence with the second code-demodulated sample to produce a second demodulated data sequence;
• and
• a fourth accumulator coupled to the fourth multiplier, the fourth accumulator configured to sum the second demodulated data sequence to produce a second intermediate output data sample.