Mixed-signal radio frequency receiver implementing multi-mode spur avoidance

A spur avoidance circuit in a mixed-signal radio frequency (RF) receiver where the RF receiver is coupled to receive an incoming RF signal and to generate at least a processed digital output signal, the RF receiver including at least an RF-Analog front end circuit, an analog-to-digital converter (ADC) and a digital signal processor (DSP), the spur avoidance circuit comprising:

• a clock synthesizer circuit configured to generate a first clock signal having a first clock frequency;
• a clock generator circuit configured to receive the first clock signal and to generate a second clock signal to control the ADC, a third clock signal to control the DSP and a fourth clock signal, the second, third and fourth clock signals having respective second, third and fourth clock frequencies related to the first clock frequency, wherein, in selected operation modes, the clock generator circuit is further configured to apply a jitter sequence to jitter the second and/or third clock frequency around a mean frequency value based on a predictable, periodic pseudo-random number sequence;
• an input buffer configured to receive input data from the ADC and to store the input data, the input buffer having a write port being driven by the second clock signal and a read port being driven by the third clock signal;
• an input sample rate converter configured to receive input data from the input buffer or the ADC at an input sampling rate and to generate output data at an output sampling rate being a uniform sampling rate, the input sample rate converter configured to provide the output data to the DSP;
• an output sample rate converter configured to receive input data from the DSP at an input sampling rate being a uniform sample rate and to generate output data at an output sampling rate matching the fourth clock frequency;
• an output buffer configured to receive input data from the DSP or the output sample rate converter and to store the input data, the output buffer having a write port being driven by the third clock signal and a read port being driven by the fourth clock signal;
• and
• a plurality of bypass signal paths coupled to each of circuit elements including the input buffer, the input sample rate converter, the output sample rate converter and the output buffer, the plurality of bypass signal paths being selectively activated to bypass one or more of the circuit elements coupled thereto, wherein the DSP receives input data either from the ADC, or from the input buffer, or from the input sample rate converter;
• and the DSP providing output data to either the output sample rate converter, to the output buffer or as the processed digital output signal,
• wherein the spur avoidance circuit is configured to operate in one or more operation modes selected from a plurality of operation modes using the plurality of bypass signal paths to select or bypass one or more of the circuit elements, the spur avoidance circuit is operated in a first set of operation modes to shift the second, third, and fourth clock frequencies out of a wanted signal channel of the RF receiver and is configured in a second set of operation modes to spread the clock frequency of at least the third clock signal based on the predictable, periodic pseudo-random number sequence.