High speed counter design
AssigneeFoundry Networks, Inc.
InventorsYuen Fai Wong, Hui Zhang
Life of this patent
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Abstract
Techniques for incrementing counters in an efficient manner. In one set of embodiments, counter logic circuits are provided that can operate at higher frequencies than existing counter logic circuits, while being capable of being implemented in currently available field programmable gate arrays (FPGAs) or fabricated using currently available process technologies. The counter logic circuits of the present invention may be used to increment statistics counters in network devices that support line speeds of 40 Gbps, 100 Gbps, and greater.
Claims27
A method for incrementing a counter in a logic circuit, the method comprising:
- receiving a stream comprising a plurality of index/value pairs, each index/value pair including a counter index referencing a counter value to be incremented and an increment value;
- determining two or more index/value pairs in the stream that include a common counter index;
- and
- causing the stream to include an index/value pair including the common counter index and an increment value corresponding to a sum of the increment values included in the two or more index/value pairs.
A logic circuit for incrementing a counter, the logic circuit comprising:
- a fusion component configured to:
- receive a stream comprising a plurality of index/value pairs, each index/value pair including a counter index referencing a counter value to be incremented and an increment value;
- determine two or more index/value pairs in the stream that include a common counter index;
- and
- cause the stream to include an index/value pair including the common counter index and an increment value corresponding to a sum of the increment values included in the two or more index/value pairs.
A network device comprising:
- a logic circuit for incrementing a counter, the logic circuit including a fusion component configured to:
- receive a stream comprising a plurality of index/value pairs, each index/value pair including a counter index referencing a counter value to be incremented and an increment value;
- determine two or more index/value pairs in the stream that include a common counter index;
- and
- cause the stream to include an index/value pair including the common counter index and an increment value corresponding to a sum of the increment values included in the two or more index/value pairs.
Dependencies are inferred from the claim text.