US 8,576,655 B2 · Semiconductor memories

Abstract

A semiconductor memory includes a bit cell having first and inverters forming a latch. First and second transistors are respectively coupled to first and second storage nodes of the latch and to first and second write bit lines. Each of the first and second transistors has a respective gate coupled to a first node. Third and fourth transistors are coupled together in series at the first node and are disposed between a write word line and a first voltage source. Each of the first and second transistors has a respective gate coupled to a first control line. A fifth transistor has a source coupled to a second voltage source, a drain coupled to at least one of the inverters of the latch, and a gate coupled to the first node. A read port is coupled to a first read bit line and to the second storage node of the latch.

Claims20

Dependent claims

A semiconductor memory, comprising:

a memory bit cell including:
a first storage node coupled to an input of a first inverter and to an output of a second inverter;
a second storage node coupled to an output of the first inverter and to an input of the second inverter;
a first transistor coupled to the first storage node and to a first write bit line;
a second transistor coupled to the second storage node and to a second write bit line;
a third transistor having a source coupled to a first voltage supply and to the first inverter;
a fourth transistor having a drain coupled to a second voltage source, a gate coupled to a first control line, and a source coupled to a first node;
a third inverter having an input coupled to a first control line and an output coupled to the gates of the first, second, and third transistors;
and
a read port coupled to a first read bit line and to the second storage node.

7 more elements

Dependencies are inferred from the claim text.

Semiconductor memories

Life of this patent

Semiconductor memories

Life of this patent

Abstract

Claims20