Semiconductor memory device, memory system including memory controller, and refresh control method for a semiconductor memory device
AssigneeElpida Memory, Inc.
InventorAtsuo Koshizuka
Life of this patent
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Abstract
A semiconductor memory device has an operation mode in which a read/write operation is performed in response to a command supplied externally in synchronization with a clock, and a power-down mode in which no external read/write command is accepted. The semiconductor memory device performs a refresh operation in response to an externally supplied signal during the power-down mode. A memory system has a plurality of the semiconductor devices and a memory controller. The memory controller outputs a control signal during the power-down mode, and the plurality of semiconductor devices perform a refresh operation in response to the control signal during the power-down mode.
Claims9
A memory controller connected to a semiconductor device including a memory cell, the memory controller comprising:
- a memory control unit that, during a operation mode that allows said semiconductor device to deal with an access to information data from outside, periodically outputs a command that permits said semiconductor device to perform a refresh operation for data written in said memory cell;
- and
- a power-down mode refresh control unit that, during a power-down mode that inhibits said semiconductor device from dealing with access to said information data from outside, periodically outputs a first signal, different from said command, to said semiconductor device to execute said refresh operation,
- wherein, in case said semiconductor device is set to said power down mode, in which said semiconductor memory device does not accept said command, said power-down mode refresh control unit outputs said first signal to one of input buffers of said semiconductor memory device which is able to accept a signal from outside of said semiconductor memory device even during said power-down mode.
A memory system comprising:
- a semiconductor device and a memory controller that controls said semiconductor device;
- wherein
- said semiconductor device includes a memory cell array having a plurality of information data;
- and a plurality of input buffers;
- said semiconductor device receiving a command that allows said semiconductor device to execute an access to said information data from outside, a clock signal that synchronously controls said command, a chip select signal that selects said semiconductor device and a clock enable signal that internally invalidates said clock signal to inhibit said semiconductor device from dealing with an access to said information data from outside;
- and wherein
- in case said semiconductor device is in an operation mode that allows said semiconductor device to deal with access to said information data from outside, said memory controller outputs said command, said clock signal, said chip select signal and the clock enable signal to said semiconductor device and periodically issues a command for refreshing data retained in said memory cell array;
- said memory controller in case said semiconductor device is in a power down mode that inhibits said semiconductor device from dealing with an access to said information data from outside, refreshing said memory cell array based on said clock enable signal and on said chip select signal that is periodically issued, and outputting a signal to execute a refresh operation to one of said plurality of input buffers of said semiconductor memory device which is able to accept a signal from outside of said semiconductor memory device even during said power down mode.
Dependencies are inferred from the claim text.