Temperature compensation of conductive bridge memory arrays

A method for operating a non-volatile semiconductor memory array, comprising:

• detecting a first condition associated with the semiconductor memory array, the semiconductor memory array comprises a cross-point memory array, the detecting a first condition includes at least one of detecting a particular temperature associated with the semiconductor memory array or detecting a particular number of write cycles associated with the semiconductor memory array, the semiconductor memory array includes a plurality of word lines arranged in a first direction and a plurality of bit lines arranged in a second direction, the plurality of word lines includes a first word line and one or more other word lines, the plurality of bit lines includes a first bit line and one or more other bit lines, the semiconductor memory array includes a first semiconductor storage element disposed between the first word line and the first bit line;
• applying a selected word line voltage to the first word line;
• applying one or more intermediate voltages based on the first condition to the one or more other word lines and the one or more other bit lines;
• and
• setting the first semiconductor storage element into a first state in response to the applying a selected word line voltage.

A non-volatile storage system, comprising:

• a semiconductor memory array, the semiconductor memory array comprises a cross-point memory array and includes a plurality of word lines arranged in a first direction and a plurality of bit lines arranged in a second direction, the plurality of word lines includes a first word line and one or more other word lines, the plurality of bit lines includes a first bit line and one or more other bit lines, the semiconductor memory array includes a first semiconductor storage element disposed between the first word line and the first bit line;
• a first voltage reference circuit, the first voltage reference circuit generates one or more intermediate voltages based on a temperature associated with the semiconductor memory array;
• a second voltage reference circuit, the second voltage reference circuit generates a selected word line voltage based on the temperature;
• and
• one or more managing circuits in communication with the plurality of word lines and the plurality of bit lines, the one or more managing circuits bias the one or more other word lines to the one or more intermediate voltages and bias the one or more other bit lines to the one or more intermediate voltages, the one or more managing circuits bias the first word line to the selected word line voltage and bias the first bit line to a selected bit line voltage.