Method for semiconductor memory interface device with noise cancellation circuitry having phase and gain adjustments
AssigneeSamsung Electronics Co., Ltd.
InventorsTae-Young Oh, Seung-Jun Bae, Kwnag-Il Park
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Abstract
A memory interface circuit is provided, comprising: a first signal output circuit configured to output a first signal via a first signal line to a first I/O terminal; a second signal output circuit configured to output a second signal via a second signal line to a second I/O terminal; and a noise cancellation circuit having at least one phase adjusting element and at least one gain adjusting element to reduce a noise signal induced on the second signal line due to the presence of the first signal on the first signal line, wherein the second signal line is disposed adjacent to the first signal line.
Claims15
A memory interface method, comprising:
- detecting a noise signal at a second signal line induced from a signal on a first signal line disposed adjacent to the second signal line;
- measuring the phase and magnitude of the noise signal;
- adjusting delay and gain values of a noise cancellation circuit based on the measured phase and magnitude of the noise signal to output a noise reduction signal;
- and
- applying the noise reduction signal to the second signal line to reduce the noise signal present at the second signal line.
A method of noise reduction training in a memory device, comprising:
- transmitting a signal through a first signal line;
- measuring characteristics of a noise signal generated on a second signal line;
- generating a noise reduction signal by adjusting the phase of the measured noise signal;
- repeating the measuring and generating steps until the noise level is within a predetermined level;
- and
- applying the noise reduction signal to the second signal line.
A memory interface method, comprising:
- detecting first noise signals at second and third signal lines induced from a signal on a first signal line;
- measuring phases and magnitudes of the first noise signals;
- detecting second noise signals at first and second signal lines induced from a signal on the first signal line;
- measuring phases and magnitudes of the second noise signals;
- adjusting delay and gain values of a first noise cancellation circuit based on the measured phase and magnitude of the first noise signals to output a first noise reduction signal;
- adjusting delay and gain values of a second noise cancellation circuit based on the measured phase and magnitude of the second noise signals to output a second noise reduction signal;
- and
- applying the first noise reduction signal to the second and third signal lines and applying the second noise reduction signal to the first and second signal lines respectively.
Dependencies are inferred from the claim text.