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US 8,576,649 B1Granted
Sense amplifiers and operations thereof
OwnerFarid Nematiinventor
Life of this patent
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Abstract
Sense amplifiers and operations thereof are described. More particularly, embodiments of integrated circuit having a sense amplifier coupled to a first bitline and a second bitline of a memory array are described. The sense amplifier generally includes: a latch circuit and a group select input/output circuit, as well as read, reference voltage, and precharge circuitry. Further described is an embodiment of a method for a refresh operation. First data states of a group of memory cells of an array are read and written back as second data states without changing voltages at sense nodes of the latch circuits from the reading, where the second data states are an inverse of the first data states.
Claims29
An integrated circuit, comprising:
- a sense amplifier coupled to a first bitline and a second bitline of a memory array;
- wherein the sense amplifier includes:
- a latch circuit having a first sense amplifier node and a second sense amplifier node respectively coupled to the first bitline and the second bitline;
- a group select input/output circuit coupled to the first sense amplifier node and the second sense amplifier node;
- and
- a read-precharge-reference voltage circuit coupled to the first sense amplifier node and the second sense amplifier node;
- wherein the read-precharge-reference circuit includes:
- a first transistor coupled between a first reference voltage and the first sense amplifier node for pass gating, the first transistor gated with a first read signal;
- and
- a second transistor coupled between a second reference voltage and the second sense amplifier node for pass gating, the second transistor gated with a second read signal;
- a first bit voltage select circuit coupled between the first sense amplifier node and the first bitline;
- a second bit voltage select circuit coupled between the second sense amplifier node and the second bitline;
- wherein the first bit voltage select circuit includes a third transistor coupled between the first sense amplifier node and the first bitline for pass gating;
- wherein the first bit voltage select circuit further includes a fourth transistor commonly gated with the third transistor to receive a first select signal, the fourth transistor having a first source/drain node coupled to receive a bit voltage and a second source/drain node coupled to the first bitline;
- wherein the second bit voltage select circuit includes a fifth transistor coupled between the second sense amplifier node and the second bitline for pass gating;
- and
- wherein the second bit voltage select circuit further includes a sixth transistor commonly gated with the fifth transistor to receive a second select signal, the sixth transistor having a first source/drain node coupled to receive the bit voltage and a second source/drain node coupled to the second bitline.
14 more elements
An integrated circuit, comprising:
- a sense amplifier coupled to a first bitline and a second bitline of the memory array;
- the sense amplifier including:
- a latch circuit having a first sense amplifier node and a second sense amplifier node respectively coupled to the first bitline and the second bitline;
- a group select input/output circuit coupled to the first sense amplifier node and the second sense amplifier node;
- and
- a reference voltage circuit, a read circuit, and a precharge circuit coupled in parallel with one another to the first sense amplifier node and the second sense amplifier node.
3 more elements
An integrated circuit, comprising:
- a sense amplifier coupled to a first bitline and a second bitline of the memory array;
- the sense amplifier including:
- a latch circuit having a first sense amplifier node and a second sense amplifier node respectively coupled to the first bitline and the second bitline;
- a group select input/output circuit coupled to the first sense amplifier node and the second sense amplifier node;
- and
- a reference voltage circuit and a read circuit coupled in parallel with one another to the first sense amplifier node and the second sense amplifier node.
3 more elements
An integrated circuit, comprising:
- a sense amplifier coupled to a first bitline and a second bitline of the memory array;
- the sense amplifier including:
- a latch circuit having a first sense amplifier node and a second sense amplifier node respectively coupled to the first bitline and the second bitline;
- a group select input/output circuit coupled to the first sense amplifier node and the second sense amplifier node;
- and
- a first transistor having a first source/drain node coupled to the first sense amplifier node and having a second source/drain node coupled to an intermediate node, the first transistor gated with a first sample signal;
- a second transistor having a first source/drain node coupled to the second sense amplifier node and having a second source/drain node coupled to a reference voltage, the second transistor gated with a second sample signal;
- a third transistor having a first source/drain node coupled to the intermediate node and having a second source drain node coupled to a supply voltage, the third transistor gated with a read signal;
- a first bit voltage select circuit coupled between the intermediate node and the first bitline;
- and
- a second bit voltage select circuit coupled between the intermediate node and the second bitline.
8 more elements
An integrated circuit, comprising:
- a sense amplifier coupled to a first bitline and a second bitline of the memory array;
- the sense amplifier including:
- a latch circuit having a first sense amplifier node and a second sense amplifier node respectively coupled to the first bitline and the second bitline;
- a group select input/output circuit coupled to the first sense amplifier node and the second sense amplifier node;
- a first transistor having a first source/drain node coupled to the first sense amplifier node and having a second source/drain node coupled to a bitline, the first transistor gated with a first sample signal;
- a second transistor having a first source/drain node coupled to the second sense amplifier node and having a second source/drain node coupled to a reference voltage, the second transistor gated with a second sample signal;
- a third transistor having a first source/drain node coupled to the bitline and having a second source drain node coupled to a supply voltage, the third transistor gated with a read signal;
- and
- a fourth transistor having a first source/drain node coupled to the bitline and having a second source/drain node coupled to a bit voltage, the fourth transistor gated with a precharge signal.
6 more elements
Dependencies are inferred from the claim text.