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US 8,576,645 B2Granted
Semiconductor memory device capable of minimizing current consumption during high speed operation
AssigneeHynix Semiconductor Inc.
InventorTae-Kyun Kim
Life of this patent
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Abstract
A semiconductor memory device includes a signal processing unit configured to generate a control signal corresponding to burst length information and an output controlling unit configured to control an output of a data strobe signal in response to the control signal.
Claims26
A semiconductor memory device comprising:
- a signal processing unit configured to receive a data strobe signal and generate a control signal corresponding to burst length information in an on-die-termination (ODT) mode;
- an output controlling unit configured to control an output timing of the data strobe signal in response to the control signal;
- and
- a monitoring unit configured to monitor a time interval between column commands to output a monitoring signal;
- wherein the signal processing unit deactivates the control signal in response to the monitoring signal when the time interval between the column commands is determined to equal a first time interval.
2 more elements
A semiconductor memory device comprising:
- a first input unit configured to output an internal data strobe signal in response to an external data strobe signal;
- an enable signal generating unit configured to generate an enable signal according to the external data strobe signal and termination resistance information;
- a filtering signal generating unit configured to generate a filtering signal in response to the internal data strobe signal, the enable signal, an internal on-die-termination (ODT) mode entry signal, an ODT mode related signal comprising burst length information, and an internal clock;
- and
- an output controlling unit configured to receive the internal data strobe signal and stop an output period of the internal data strobe signal in response to the filtering signal.
2 more elements
Dependencies are inferred from the claim text.