Memory devices having controllers that divide command signals into two signals and systems including such memory devices
AssigneeSamsung Electronics Co., Ltd.
InventorsSeong Hyun Jeon, Hoi Ju Chung, Jung Sunwoo
Life of this patent
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Abstract
A memory device using error correcting code and a system including the same are provided. The memory device includes a memory cell array including a plurality of bit lines and a plurality of memory cells; an access block for accessing the memory cell array; and a controller block for receiving a first operation command signal, dividing the first operation command signal into at least two paths pulse signals corresponding to at least two paths, based on a pre-determined criterion, and then supplying the at least two path pulse signals to the access block. The access block operates based on an output signal of the controller block.
Claims23
A memory device comprising:
- a memory cell array including a plurality of bit lines and a plurality of memory cells;
- an access block that is configured to access the memory cell array;
- and
- a controller that is configured to receive a first operation command signal, and divide the first operation command signal into at least a first path pulse signal that is transmitted on a first path and a second path pulse signal that is transmitted on a second path based on a predetermined criterion,
- wherein the access block operates based on an output signal of the controller,
- wherein the first and second path pulse signals are output to the access block.
A memory device comprising:
- a memory cell array that includes a data cell region that is configured to store data or data bits and an error correcting code (ECC) cell region that is configured to store ECC bits;
- an access block that is configured to access the memory cell array;
- and
- a controller that is configured to receive at least first and second operation command signals, and divide each of the first and second operation command signals into first and second path pulse signals that correspond to first and second paths based on a predetermined criterion,
- wherein the access block operates in response to an output signal of the controller,
- wherein the first and second path pulse signals are output to the access block.
A memory device, comprising:
- a memory cell array that includes a plurality of bit lines and a plurality of memory cells;
- an access block that is configured to access the memory cells via the plurality of bit lines;
- a controller that is configured to selectively route a plurality of pulses that are included in one or more operation command signals to one of a first path or a second path in response to a selection signal;
- and
- a combiner that is configured to combine a first signal that is output from the first path and a second signal that is output from the second path and to supply the combined signal to the access block;
- a first group of pulse generators that are connected in series, wherein a third pulse generator that is on an end of the first group of pulse generators receives the combined signal, and
- wherein a value of the selection signal is based on whether an interval between a first logic high signal of the one or more operation command signals and a second logic high signal of the one or more operation command signals is less than or equal to a predetermined interval.
A method of providing first and second read commands to an access block of a memory device, the method comprising:
- transmitting the first read command on a first path;
- transmitting the second read command on a second path;
- increasing a pulse width of the first read command to provide a modified first read command;
- and
- providing the modified first read command to the access block.
Dependencies are inferred from the claim text.