Method of using multiplexing circuit for high speed, low leakage, column-multiplexing memory devices

A method of outputting data using a multiplexer, the multiplexer having a plurality of sub-circuits, each of the plurality of sub-circuits comprising a first transistor, a second transistor, and a third transistor, the method comprising:

• turning on the second transistor of a selected one of the plurality of sub-circuits responsive to a clock signal and address information;
• turning off the second transistor of a non-selected one of the plurality of sub-circuits;
• turning on a fourth transistor responsive to the clock signal, the fourth transistor having a first terminal coupled with drains of the first transistors of the plurality of sub-circuits and a second terminal coupled with drains of the second transistors of the plurality of sub-circuits;
• and
• coupling the first terminal of the fourth transistor to a first power node via the first transistor of the selected one of the plurality of sub-circuits or to a second power node via the second and third transistors of the selected one of the plurality of sub-circuits responsive to a corresponding read data signal.

A method of operating a multiplexer, the multiplexer having a plurality of sub-circuits, each of the plurality of sub-circuits comprising a first P-type transistor, a first N-type transistor, and a second N-type transistor, drains of the first P-type transistors coupled with a drain of a third N-type transistor, and drains of the first N-type transistors coupled with a source of the third N-type transistor, the method comprising:

• turning on the first N-type transistor of a selected one of the plurality of sub-circuits responsive to a clock signal and address information;
• turning off the first N-type transistor of a non-selected one of the plurality of sub-circuits;
• turning on the third N-type transistor responsive to the clock signal;
• and
• coupling the drain of the third N-type transistor to a first power node via the first P-type transistor of the selected one of the plurality of sub-circuits or to a second power node via the first and second N-type transistors of the selected one of the plurality of sub-circuits responsive to a corresponding read data signal.