Memory device having switch providing voltage to bit line
AssigneeElpida Memory, Inc.
InventorGiulio Martinozzi
Life of this patent
Estimating the term…
Abstract
A memory device in which a circuit reads a cell condition. A terminal provides voltage to a bit line of the circuit via a switch. The circuit outputs and enables storage of a first logical value when the voltage provided from the terminal does not exceed a threshold value. The circuit outputs and enables storage of a second logical value when the voltage provided from the terminal exceeds the threshold value. The output and storage occurs in the absence of an electrical connection between the cell and circuit. The switch provides voltage supplied from the terminal to the bit line of the circuit. The voltage increases from a value which does not exceed the threshold to a value which exceeds the threshold.
Claims20
A memory device comprising:
- a circuit configured to read a condition of a cell, and
- a terminal configured to provide voltage to a bit line of the circuit via a switch,
- the circuit being configured to, in the absence of an electrical connection between the cell and circuit, output and enable storage of a first logical value when the voltage provided from the one terminal does not exceed a threshold value and to output and enable storage of a second logical value when the voltage provided from the one terminal exceeds the threshold value, and
- the switch being configured to provide voltage supplied from the terminal to the bit line of the circuit which increases from a voltage which does not exceed the threshold value to a voltage which exceeds the threshold value.
A method of testing a memory device comprising:
- performing a test operation by applying a first voltage to a circuit configured to read a cell condition and enable storage of a logical value associated with the cell condition,
- performing a read operation by reading the logical value that is outputted and stored by the circuit without requiring an electrical connection with the cell, and
- repeating the test operation with a second voltage, the second voltage being higher than the first voltage.
A device comprising:
- a first bit line associated with a first memory cell;
- a second bit line associated with a second memory cell;
- a bias node;
- a first transistor coupled between the bias node and the first bit line;
- a second transistor coupled between the bias node and the second bit line;
- a sensing transistor including a gate;
- a third transistor coupled between the gate of the sensing transistor and the first bit line;
- a fourth transistor coupled between the gate of the sensing transistor and the second bit line;
- an external pad;
- and
- a switch between the pad and the bias node, controlled by a test signal.
Dependencies are inferred from the claim text.