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US 8,576,627 B2Granted
Memory array with inverted data-lines pairs
AssigneeMicron Technology, Inc.
InventorSatoru Tamada
Life of this patent
Estimating the term…
Abstract
At least one data-line pair has a first data line aligned with a first column of memory cells and a second data line aligned with a second column of memory cells. The first data line is coupled to the second column of memory cells and the second data line is coupled to the first column of memory cells.
Claims20
A memory array, comprising:
- a first column of memory cells coupled to a first data line;
- a second column of memory cells coupled to a second data line;
- a third column of memory cells coupled to a third data line;
- wherein the second column of memory cells is between the first and third columns of memory cells;
- and
- wherein the third data line is between the first and second data lines.
3 more elements
A method of programming a memory array, comprising:
- applying a first voltage differential across a first memory cell coupled to an access line;
- applying a second voltage differential across a second memory cell coupled to the access line while applying the first voltage differential across the first memory cell;
- and
- applying a third voltage differential across a third memory cell coupled to the access line while applying the first voltage differential across the first memory cell and while applying the second voltage differential across the second memory cell;
- wherein the first voltage differential is less than the second voltage differential and the second voltage differential is less than the third voltage differential.
2 more elements
A method of programming a memory array, comprising:
- applying a first voltage at a first level of the first voltage to an access line coupled to a memory cell of each of first, second, and third columns of memory cells;
- applying a second voltage at a first level of the second voltage to a channel of the memory cell of the first column while applying the first voltage to the access line;
- applying a third voltage at a first level of the third voltage to a channel of the memory cell of the second column while applying the second voltage to the channel of the memory cell of the first column;
- applying a fourth voltage to a channel of the memory cell of the third column while applying the second voltage to the channel of the memory cell of the first column and while applying the third voltage to the channel of the memory cell of the second column;
- increasing the first level of the first voltage applied to the access line to a second level of the first voltage applied to the access line;
- allowing the second level of the first voltage applied to the access line to, at least in part, boost the first level of the second voltage applied to the channel of the memory cell of the first column to a second level of the second voltage applied to the channel of the memory cell of the first column;
- allowing the second level of the first voltage applied to the access line to, at least in part, boost the first level of the third voltage applied to the channel of the memory cell of the second column to a second level of the third voltage applied to the channel of the memory cell of the second column;
- and
- substantially preventing the second level of the first voltage applied to the access line from changing the fourth voltage applied to the channel of the memory cell of the third column.
6 more elements
Dependencies are inferred from the claim text.