Non-volatile semiconductor storage device
AssigneeKabushiki Kaisha Toshiba
InventorHidefumi Nawata
Life of this patent
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Abstract
A non-volatile semiconductor storage device according to one embodiment includes a memory cell array that has NAND cell units in which a plurality of memory cells are connected in series, the control gate of each of the plurality of memory cells being connected to a word line, and a control circuit configured to execute a write operation by applying a write voltage to the word line. The control circuit is configured to execute a correction write operation accompanied by the write operation and executed on a selected memory cell, when a threshold voltage of data written in a reference memory cell is an erase level, the reference memory cell being the memory cell adjacent to the selected memory cell and in which the data is written after the write operation on the selected memory cell.
Claims20
A non-volatile semiconductor storage device, comprising:
- a memory cell array that has NAND cell units in which a plurality of memory cells each having a control gate and a charge accumulating layer are connected in series, one end of the NAND cell unit being connected to a bit line through a first select gate transistor, the other end thereof being connected to a source line through a second select gate transistor, the control gate of each of the plurality of memory cells being connected to a word line and gates of the first and second select gate transistors being respectively connected to first and second select gate lines;
- and
- a control circuit configured to execute a write operation by applying a write voltage to the word line to set a threshold voltage of a selected memory cell corresponding to data, and a correction write operation accompanied by the write operation and executed on the selected memory cell, when a threshold voltage of data written in a reference memory cell is an erase level, the reference memory cell being the memory cell adjacent to the selected memory cell and in which the data is written after the write operation on the selected memory cell.
A non-volatile semiconductor storage device, comprising:
- a memory cell array that has NAND cell units in which a plurality of memory cells each having a control gate and a charge accumulating layer are connected in series, one end of the NAND cell unit being connected to a bit line through a first select gate transistor, the other end thereof being connected to a source line through a second select gate transistor, the control gate of each of the plurality of memory cells being connected to a word line and gates of the first and second select gate transistors being respectively connected to first and second select gate lines;
- and
- a control circuit configured to execute a write operation by applying a write voltage to the word line to set a threshold voltage of a selected memory cell corresponding to data,
- the control circuit being configured to control whether a correction write operation accompanied by the write operation is executed on the selected memory cell depending on data written in a reference memory cell, the reference memory cell being the memory cell adjacent to the selected memory cell and in which the data is written after the write operation on the selected memory cell.
A non-volatile semiconductor storage device, comprising:
- a memory cell array that has NAND cell units in which a plurality of memory cells each having a control gate and a charge accumulating layer are connected in series, one end of the NAND cell unit being connected to a bit line through a first select gate transistor, the other end thereof being connected to a source line through a second select gate transistor, the control gate of each of the plurality of memory cells being connected to a word line and gates of the first and second select gate transistors being respectively connected to first and second select gate lines;
- and
- a control circuit configured to execute a write operation by applying a write voltage to the word line to set a threshold voltage of a selected memory cell corresponding to data,
- the control circuit being configured to control a read voltage depending on data written in a reference memory cell, the read voltage being applied to a word line connected to a memory cell adjacent to the selected memory cell when the verification read operation is executed at the time of the correction write operation accompanied with the write operation, the reference memory cell being the memory cell adjacent to the selected memory cell and in which the data is written after the write operation on the selected memory cell.
Dependencies are inferred from the claim text.