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US 8,576,619 B2Granted
Phase change random access memory apparatus performing a firing operation
AssigneeSK hynix Inc.
InventorsJung Hyuk Yoon, Dong Keun Kim
Life of this patent
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Abstract
A phase change random access memory (PCRAM) apparatus includes: a memory cell array including a plurality of phase change memory cells; and a firing control unit configured to provide a firing voltage for firing the plurality of phase change memory cells to a global bit line in response to an enable signal based on a test mode signal.
Claims21
A phase change random access memory (PCRAM) apparatus comprising:
- a memory cell array comprising a plurality of phase change memory cells;
- a firing control unit configured to provide a firing voltage for firing the plurality of phase change memory cells to a global bit line in response to an enable signal based on a test mode signal;
- a second switching unit configured to electrically connect the memory cell array with a write driving unit through the global bit line during a write operation and electrically disconnect the memory cell array with the write driving unit during a firing operation;
- and
- the write driving unit configured to receive a high voltage and provide a write signal to the memory cell array utilizing the high voltage when the write driving unit is electrically connected with the memory cell array.
2 more elements
A PCRAM apparatus comprising:
- a memory cell array comprising a plurality of phase change memory cells;
- a write driving unit configured to receive a high voltage and provide a write signal to the plurality of phase change memory cells utilizing the high voltage when the write driving unit is electrically connected with the plurality of phase change memory cells;
- a firing control unit configured to provide a firing voltage for firing the plurality of phase change memory cells to a global bit line in response to an enable signal based on a test mode signal during a firing operation;
- and
- a second switching unit configured to electrically connect the memory cell array with the write driving unit through the global bit line during a write operation and electrically disconnect the memory cell array with the write driving unit during the firing operation.
2 more elements
Dependencies are inferred from the claim text.