Tunnel transistor, logical gate including the transistor, static random-access memory using the logical gate and method for making such a tunnel transistor

A tunnel transistor, comprising:

• a drain electrode;
• a source electrode;
• a drain comprising a first semiconductor part doped with n-type dopants in electrical contact with the drain electrode;
• a source comprising a second semiconductor part doped with p-type dopants in electrical contact with the source electrode;
• a first gate comprising a first gate dielectric material adjacent to the first semiconductor part along and contacting, with a first side of the first gate dielectric material;
• and
• a second gate separate from the first gate and configured to control a current between the drain and the source, the second gate comprising a second gate dielectric material adjacent to the second semiconductor part along and contacting, with a first side of the second gate dielectric material,
• wherein the first semiconductor part is situated at a first side of the tunnel transistor and the first gate electrode is situated along the first gate dielectric material and opposing the first side of the first gate dielectric material,
• wherein the drain and the source are positioned adjacently to each other along a contact region of the tunnel transistor, wherein the contact region longitudinally extends along an extending direction,
• wherein the second semiconductor part at a second side of the tunnel transistor and a second gate electrode along the second gate dielectric material and opposing the first side of the second gate dielectric material, the first and the second gate are configured to control current between a substantially conducting state and a substantially isolating state between the drain and the source by an electrical potential difference between the first and the second gate generating a gate-induced electric field between the first and the second gate, wherein the first and second gate electrode are positioned substantially along respectively the first and the second semiconductor part, and
• wherein the first and the second gate, with respect to each other and with respect to the first and the second semiconductor part, are configured such that an electric field, induced by the electrical potential difference between the first and the second gate, is created through the contact region such that the field lines of the electric field intersect with the extending direction.