Low leakage high performance static random access memory cell using dual-technology transistors

A memory cell, comprising:

• a storage element comprising a first n-channel field effect transistor (NFET), a second NFET, a first p-channel field effect transistor (PFET), and a second PFET, wherein the source terminal of the first NFET and the source terminal of the second NFET are coupled to a ground potential and the source terminal of the first PFET and the source terminal of the second PFET are coupled to a first potential, wherein the gate terminal of the first NFET is coupled to the gate terminal of the first PFET, wherein the gate terminal of the second NFET is coupled to the gate terminal of the second PFET, wherein the drain terminal of the first NFET is coupled to the drain terminal of the first PFET, wherein the drain terminal of the second NFET is coupled to the drain terminal of the second PFET, wherein the gate terminal of the first NFET and the gate terminal of the first PFET are coupled to the drain terminal of the second NFET and to the drain terminal of the second PFET, and wherein the gate terminal of the second NFET and the gate terminal of the second PFET are coupled to the drain terminal of the first NFET and to the drain terminal of the first PFET;
• a write circuit comprising a third NFET and a fourth NFET, wherein the gate terminal of the third NFET and the gate terminal of fourth NFETs are coupled together and are adapted to be coupled to a write word line, wherein the source terminals of the third NFET and the fourth NFET are each adapted to be coupled to one of a pair of complementary bit lines, wherein the drain terminal of the third NFET is coupled to the gate terminal of the first NFET and to the gate terminal of the first PFET, and wherein the drain terminal of the fourth NFET is coupled to the gate terminal of the second NFET and to the gate terminal of the second PFET;
• and
• a read circuit comprising a fifth NFET and a sixth NFET, wherein the source terminal of the fifth NFET is coupled to the ground potential, wherein the gate terminal of the fifth NFET is coupled to the drain terminal of the first NFET and to the drain terminal of the first PFET, wherein the drain terminal of the fifth NFET is coupled to the source terminal of the sixth NFET, wherein the gate terminal of the sixth NFET is adapted to be coupled to a read word line, wherein the first PFET of the storage element, the second PFET of the storage element, the first NFET of the storage element, and the second NFET of the of the storage element are fabricated using a first functional gate oxide having a first thickness, and wherein the fifth NFET of the read circuit and the sixth NFET of the read circuit are fabricated using a second functional gate oxide having a second thickness that is less than the first thickness.

A memory cell, comprising:

• means for storing data;
• means for writing data into the means for storing data, the means for writing data coupled to the means for storing data;
• and
• means for reading data from the means for storing data, wherein the means for reading data includes a first transistor and a second transistor;
• wherein at least a portion of the means for storing data and at least a portion of the means for writing data are fabricated using a first functional gate oxide having a first thickness, wherein the first transistor of the means for reading data is coupled to the means for storing data, wherein the second transistor of the means for reading data is coupled to the first transistor of the means for reading data, and wherein the first transistor of the means for reading data and the second transistor of the means for reading data are fabricated using a second functional gate oxide having a second thickness that is less than the first thickness.

A memory array comprising a plurality of memory cells, wherein at least one memory cell comprises:

• a storage element;
• a write circuit coupled to the storage element;
• and
• a read circuit coupled to the storage element, the read circuit including a first transistor and a second transistor;
• wherein at least a portion of the storage element and at least a portion of the write circuit are fabricated using a first functional gate oxide having a first thickness, wherein the first transistor of the read circuit is coupled to the storage element, wherein the second transistor of the read circuit is coupled to the first transistor of the read circuit, and wherein the first transistor of the read circuit and the second transistor of the read circuit are fabricated using a second functional gate oxide having a second thickness that is less than the first thickness.

A non-transitory computer-readable medium including program code that, when executed by a processor, causes the processor to:

• write to a storage element using a write circuit coupled to the storage element;
• and
• read from the storage element using a read circuit coupled to the storage element, the read circuit including a first transistor and a second transistor;
• wherein at least a portion of the storage element and at least a portion of the write circuit are fabricated using a first functional gate oxide having a first thickness, wherein the first transistor of the read circuit is coupled to the storage element, wherein the second transistor of the read circuit is coupled to the first transistor of the read circuit, and wherein the first transistor of the read circuit and the second transistor of the read circuit are fabricated using a second functional gate oxide having a second thickness that is less than the first thickness.