Semiconductor device having floating body type transistor
AssigneeElpida Memory, Inc.
InventorSoichiro Yoshida
Life of this patent
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Abstract
A semiconductor device is disclosed in which a signal line and a drive circuit driving the signal line in response to a signal to be transmitted are provided. A transistor of a floating body type is further provided that includes a gate, a source, a drain, and a body between the source and drain which is brought into an electrically floating state. The gate is connected to the signal line, and at least one of the source and drain is connected to a control node that is supplied with a control signal. The control signal is configured to receive a control signal that changes from the first level to a second level during the period of time when the drive circuit is driving the signal node.
Claims20
A semiconductor device comprising:
- a signal line;
- a control node;
- a transistor of a floating body type including a gate, a source, a drain, and a body between the source and drain, the body being brought into an electrically floating state, the gate being connected to the signal line;
- and at least one of the source and drain being connected to the control node;
- and
- a drive circuit driving the signal line in response to a signal to be transmitted;
- the control node being configured to receive a control signal that takes a first level during a period of time when the drive circuit is driving the signal node and changes from the first level to a second level during the period of time when the drive circuit is driving the signal node.
A semiconductor device comprising:
- a transmission circuit transmitting a signal to a signal line;
- an amplifier coupled to the signal line and performing an amplifying operation on a change in level of the signal line from an initial level;
- and
- a capacitor having a first electrode connected to the signal line and a second electrode supplied with a control signal, the capacitor comprising a first transistor of a floating body type including a gate, a source, a drain, and a body between the source and drain, the body being brought into an electrically floating state, the gate being connected to the first electrode, and at least one of the source and drain being connected to the second electrode;
- the first control signal being controlled during the amplifying operation by the amplifier to change from a first voltage level to a second voltage level.
A semiconductor device comprising:
- a memory cell array including a plurality of word lines, a plurality of bit lines intersecting the bit lines, and a plurality of memory cells disposed at different one of intersections of the word and bit lines;
- a plurality of sense amplifiers each coupled to an associated one of the bit lines;
- a data line;
- a switch circuit operatively coupling a selected one of the sense amplifiers to the data line;
- a data amplifier coupled to the data line and, when activated, configured to amplify a data signal appearing on the data line;
- a control node supplied with a control signal;
- and
- a transistor including a gate, a source, a drain and a body between the source and drain, the gate being connected to the data line, at least one of the source and drain being connected to the control signal node, and the body being brought into an electrically floating state;
- the control signal being changed from a first level to a second level during the data amplifier being activated.
Dependencies are inferred from the claim text.