Structure and method for biasing phase change memory array for reliable writing
AssigneeSanDisk 3D LLC
InventorRoy E. Scheuerlein
Life of this patent
Estimating the term…
Abstract
A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.
Claims20
A method for programming a plurality of memory cells in a non-volatile memory array, comprising:
- configuring a first current mirror to supply a first programming current for a first period of time;
- configuring a second current mirror to supply a second programming current for a second period of time, the second programming current is different from the first programming current;
- setting a word line connected to the plurality of memory cells to a selected word line voltage, the plurality of memory cells includes a first memory cell and a second memory cell;
- coupling the first current mirror to the first memory cell and coupling the second current mirror to the second memory cell subsequent to the setting a word line;
- and
- simultaneously programming the first memory cell and the second memory cell, the simultaneously programming includes applying the first programming current to the first memory cell for the first period of time and applying the second programming current to the second memory cell for the second period of time.
In an integrated circuit comprising an array of memory cells each comprising a memory material that is reversibly switchable from one state to another, and each connected in series between a word line and a bit line, a method of writing at least one selected memory cell while not disturbing unselected memory cells, comprising:
- controlling voltages on word lines and bit lines not connected to the at least one selected memory cell;
- controlling voltage on one of a word line and a bit line connected to the at least one selected memory cell;
- controlling current on another of the word line and bit line connected to the at least one selected memory cell;
- controlling voltage on one of the word line and bit line connected to the at least one selected memory cell comprises controlling voltage on the word line connected to the selected memory cell;
- and
- controlling current on another of the word line and bit line connected to the at least one selected memory cell comprises controlling current on the bit line connected to the at least one selected memory cell,
- wherein the voltage on the word line connected to the at least one selected memory cell is brought to a lowest voltage applied to the array of memory cells and the current on the bit line connected to the at least one selected memory cell is pulled to a value selected by a current mirror.
A non-volatile storage system including a plurality of memory cells, comprising:
- a first current mirror, the first current mirror configured to supply a first programming current for a first period of time;
- a second current mirror, the second current mirror configured to supply a second programming current for a second period of time, the second programming current is different from the first programming current;
- a word line connected to the plurality of memory cells, the plurality of memory cells includes a first memory cell and a second memory cell;
- and
- one or more control circuits in communication with the first current mirror and the second current mirror, the one or more control circuits in communication with the word line, the one or more control circuits set the word line to a selected word line voltage, the one or more control circuits cause the first current mirror to be coupled to the first memory cell and cause the second current mirror to be coupled to the second memory cell subsequent to the word line being set to the selected word line voltage, the one or more control circuits simultaneously program the first memory cell and the second memory cell by causing the first programming current to be applied to the first memory cell for the first period of time and by causing the second programming current to be applied to the second memory cell for the second period of time.
Dependencies are inferred from the claim text.