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US 8,576,607 B1Granted
Hybrid memory cell array and operations thereof
OwnerFarid Nematiinventor
Life of this patent
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Abstract
An integrated circuit and methods of operating same are described. In an embodiment of the integrated circuit included is an array of memory cells, where each of the memory cells includes a resistance-change storage element and a thyristor-based storage element coupled in series. In embodiments of the methods included are methods for data transfer, data tracking, and operating a memory array.
Claims6
An integrated circuit, comprising:
- an array of memory cells;
- each of the memory cells including a resistance-change storage element and a thyristor-based storage element coupled in series;
- wherein in first mode of operation, the thyristor-based storage elements are used as dynamic random access memory;
- and
- wherein in a second mode of operation, the thyristor-based storage element is an access device for the resistance-change storage element.
2 more elements
An integrated circuit, comprising:
- an array of first memory cells;
- and
- each of the first memory cells including a resistance-change storage element and a thyristor-based storage element coupled in series;
- wherein the array of memory cells includes:
- bitlines coupled to first contacts of the resistance-change storage elements;
- second contacts of the resistance-change storage elements coupled to corresponding first emitter regions of the thyristor-based storage elements;
- and
- second emitter regions of the thyristor-based storage elements coupled to a common wordline;
- and
- access wordlines for gating of the thyristor-based storage elements.
7 more elements
Dependencies are inferred from the claim text.