Identifying and correcting a bit error in a FRAM storage unit of a semiconductor device

Abstract

An embodiment of semiconductor device including a control unit and an FRAM storage unit is disclosed. The FRAM storage unit contains FRAM cells. The control unit includes a predetermined test data pattern. The control unit is configured to read the FRAM cells that contain a test data pattern in a margin-mode, compare the read out bit information with the test data pattern to determine whether a bit error is present in the dedicated FRAM cells. When a bit error is present, the control unit is configured to read-out the complete FRAM storage unit in a recovery-mode and refresh all FRAM cells of the FRAM storage unit by writing back the read out bit information to the respective FRAM cells. In the margin-mode, the read operation is performed using a lower read-sensitivity compared to the read operation reading out the complete FRAM storage unit that is performed in the recovery-mode.

Dependencies are inferred from the claim text.