US 8,576,603 B2 · Flash- and ROM-memory

Abstract

Method for conversion of a Flash memory cell on a first semiconductor device to a ROM memory cell in a second semiconductor device, the first and second semiconductor device each being arranged on a semiconductor substrate and each comprising an identical device portion and an identical wiring scheme for wiring the device portion to the Flash memory cell and to the ROM memory cell, respectively; the Flash memory cell being made in non-volatile memory technology and comprising an access transistor and a floating transistor, the floating transistor comprising a floating gate and a control gate; the ROM memory cell being made in a baseline technology and comprising a single gate transistor, which method includes manipulating a layout of at least one baseline mask as used in the baseline technology; the manipulation including: incorporating into the layout of the at least one baseline mask a layout of the Flash memory cell, and converting the layout of the Flash memory cell to a layout of one ROM memory cell by eliminating, from the at least one baseline mask, a layout for the floating transistor from the layout of the Flash memory cell and designating the layout of the access transistor of the Flash memory cell as a layout of the single gate transistor of the ROM memory cell.

Claims19

Dependent claims

Method for conversion of a Flash memory cell on a first semiconductor device to a ROM memory cell on a second semiconductor device, the first and second semiconductor devices each being arranged on a semiconductor substrate and each comprising an identical device portion and an identical wiring scheme for wiring the device portion to the Flash memory cell and to the ROM memory cell, respectively;

the Flash memory cell being made in non-volatile memory technology using at least one non-volatile technology mask and comprising an access transistor and a floating transistor, the floating transistor comprising a floating gate and a control gate;
the ROM memory cell being made in a baseline technology using at least one baseline mask and comprising a single gate transistor
which method includes manipulating a layout of the at least one baseline mask;
the manipulation comprising:
incorporating into a layout of the at least one baseline mask a layout of the Flash memory cell, and
converting the layout of the Flash memory cell in the at least one baseline mask to a layout of one ROM memory cell by eliminating, from the at least one baseline mask, a layout for the floating transistor from the layout of the Flash memory cell and designating a layout of the access transistor of the Flash memory cell as a layout of the single gate transistor of the ROM memory cell, wherein the Flash memory cell is paired with a second Flash memory cell that share a common contact, and the manipulation of the at least one baseline mask comprises:
elimination of a layout of the common contact from the at least one baseline mask, and creating a layout for a ROM memory cell contact at the location of the former floating transistor.

4 more elements

Second semiconductor device comprising a ROM memory cell converted from a first semiconductor device comprising a Flash memory cell;

the first and second semiconductor devices each comprising an identical device portion and an identical wiring scheme for wiring the device portion to the Flash memory cell and to the ROM memory cell, respectively, wherein the Flash memory cell has been replaced by the ROM memory cell during lithographic processing by:
incorporating into a layout of at least one baseline mask a layout of the Flash memory cell, and converting the layout of the Flash memory cell in the at least one baseline mask to a layout of the ROM memory cell by eliminating, from the at least one baseline mask, a layout for the floating transistor from the layout of the Flash memory cell and designating a layout of an access transistor of the Flash memory cell as a layout of the single gate transistor of the ROM memory cell, wherein the Flash memory cell is paired with a second Flash memory cell that share a common contact, and wherein the Flash memory cell is replaced by the ROM memory cell by:
elimination of a layout of the common contact from the at least one baseline mask, and creating a layout for a ROM memory cell contact at the location of the former floating transistor.

the Flash memory cell being made in non-volatile memory technology using at least one non-volatile technology mask and comprising an access transistor and a floating transistor, the floating transistor comprising a floating gate and a control gate;
the ROM memory cell being made in a baseline technology using at least one baseline mask and comprising a single gate transistor
which method includes manipulating a layout of the at least one baseline mask;
the manipulation comprising:
incorporating into a layout of the at least one baseline mask a layout of the Flash memory cell, and
converting the layout of the Flash memory cell in the at least one baseline mask to a layout of one ROM memory cell by eliminating, from the at least one baseline mask, a layout for the floating transistor from the layout of the Flash memory cell and designating a layout of the access transistor of the Flash memory cell as a layout of the single gate transistor of the ROM memory cell, wherein the Flash memory cell is arranged with a periphery circuitry which is arranged between the wiring scheme and the Flash memory cell for controlling operations of the Flash memory cell, and the manipulation of the at least one baseline mask comprises a modification of the at least one baseline mask for conversion of any n-channel and p-channel devices comprised by the peripheral circuitry, into baseline CMOS n-channel and p-channel devices, respectively, the modification relating to at least one of:
a layout of at least one mask for defining p-well and n-well area, a layout of a mask for defining gate oxide area, and a layout of the at least one mask for defining lightly doped area, on the second semiconductor device.

4 more elements

Dependencies are inferred from the claim text.

Flash- and ROM-memory

Life of this patent

Flash- and ROM-memory

Life of this patent

Abstract

Claims19