Semiconductor memory device and operating method thereof

Abstract

A semiconductor memory device includes a memory array configured to include memory cells for storing input data and Code Address Memory (CAM) cells for storing setting data used to set an operation condition; an operation circuit configured to perform a CAM read operation by supplying a read voltage to the CAM cells, perform a test operation for detecting unstable CAM cells in each of which a difference between a threshold voltage and the read voltage is smaller than a permitted limit, from among the CAM cells, and perform an erase operation or a program operation for the unstable CAM cells; and a controller configured to control the operation circuit so that the program operation for storing the setting data in the unstable CAM cells is performed if the number of unstable CAM cells detected in the test operation is greater than a permitted value.

Dependencies are inferred from the claim text.