Source line driving circuit, active matrix type display device and method for driving the same

A source line driver circuit of an active matrix type display device comprising:

• k (where k is an integer greater than or equal to 2) number of video signal lines to which video signals divided into a k number of signals are input;
• a shift register comprising a flip-flop, which generates and outputs a plurality of sampling pulses, in which a start pulse signal and a clock signal are input, a writing starting period is synchronized with the start pulse signal, and writing finishing periods are delayed sequentially in accordance with the clock signal;
• and
• a plurality of switches to which the source lines are connected and by which the source lines and the video signal lines conduct between each other in accordance with the sampling pulses,
• wherein the flip-flop comprises:
• a p-type transistor and a first n-type transistor, where a gate of the p-type transistor and a gate of the first n-type transistor are connected to an input of the flip-flop and the p-type transistor and the first n-type transistor are connected in series;
• a second n-type transistor connected to the first n-type transistor in series, where the clock signal is input to a gate of the second n-type transistor;
• and
• an inverter, where an input of the inverter is connected to a drain of the p-type transistor and a drain of the first n-type transistor and an output of the inverter is connected to an output of the flip-flop,
• wherein the same sampling pulse is input to the plurality of switches for every k number of the switches, and
• wherein the k number of the switches to which the same sampling pulse is input are each connected to a different one of the video signal lines.

A source line driver circuit of an active matrix type display device comprising:

• k (where k is an integer greater than or equal to 2) number of video signal lines to which video signals divided into a k number of signals are input;
• a shift register to which a start pulse signal and a clock signal are input, comprising flip-flops for a plurality of steps which generate and output a plurality of sampling pulses;
• a plurality of switches to which the source lines are connected, to which the same sampling pulse is input for every k number of switches, and by which the source lines and the video signal lines conduct between each other in accordance with the sampling pulse,
• wherein k number of the switches to which the same sampling pulse is input are each connected to a different one of the video signal lines;
• wherein the flip-flop comprises:
• a p-type transistor and a first n-type transistor, where a gate of the p-type transistor and a gate of the first n-type transistor are connected to an input of the flip-flop and the p-type transistor and the first n-type transistor are connected in series;
• a second n-type transistor connected to the first n-type transistor in series, where the clock signal is input to a gate of the second n-type transistor;
• and
• an inverter, where an input of the inverter is connected to a drain of the p-type transistor and a drain of the first n-type transistor and an output of the inverter is connected to an output of the flip-flop,
• wherein the start pulse signal is input to the input of the flip-flop of the first step,
• wherein the output of the inverter of the flip-flop of a previous step is input to the input of the flip-flop of the second step and subsequent steps, and
• wherein the sampling pulse is any one of the output of the inverter, an output of the drain of the p-type transistor, or an output of the drain of the first n-type transistor.

A driving method of an active matrix type display device including a plurality of scanning lines, a plurality of source lines intersecting with the scanning lines, and a pixel portion including a plurality of pixels connected to the scanning lines and the source lines, the method comprising:

• generating a plurality of sampling pulses in accordance with a start pulse signal, a first clock signal, and a second clock signal;
• writing a video signal to the source line in accordance with the sampling pulse;
• inputting the video signal to the pixel connected to the selected scanning line via the source line and including determination of the video signal displayed by the pixel;
• and
• generating the plurality of sampling pulses by generation of a plurality of first pulses, where a pulse width thereof is longer than half a period of the first clock signal, synchronized with the first clock signal and a plurality of second pulses, where a pulse width thereof is longer than half a period of the second clock signal, synchronized with the second clock signal, where generation alternates between generation of one of the first pulses and generation of one of the second pulses,
• wherein the period of the first clock signal and the period of the second clock signal are equal but the phase of the first clock signal and the phase of the second clock signal are different, where, for the first clock signal, either the length of a “Low” period or the length of a “High” period is longer than half the length of the period of the first clock signal and, for the second clock signal, the other of either the length of a “Low” period or the length of a “High” period is longer than half the length of the period of the second clock signal, and
• wherein the pixel portion is to be in a non-display state during a period in which the video signal is input to the pixel and the pixel portion is set from the non-display state to a display state after the video signals of all of the pixels are determined.