Method and apparatus for timing recovery
AssigneeMarvell International Ltd.
InventorJin Xie
Life of this patent
Estimating the term…
Abstract
An aspect of the disclosure provides a signal processing circuit that decouples a timing loop and an equalizer adaptation loop. The signal processing circuit includes an analog to digital converter (ADC), an equalizer, a detector, and a timing module. The ADC is configured to receive an analog signal, sample the analog signal based on a sampling clock signal, and convert the sampled analog signal into a digital signal. The equalizer is configured to equalize the digital signal. The detector is configured to detect a bit stream from the equalized digital signal. The timing module is configured to detect a timing error based on the digital signal before being equalized, and to adjust the sampling clock signal based on the timing error.
Claims20
A signal processing circuit, comprising:
- an analog to digital converter (ADC) configured to receive an analog signal, sample the analog signal based on a sampling clock signal, and convert the sampled analog signal into a digital signal;
- an equalizer configured to equalize the digital signal;
- a detector configured to detect a bit stream from the equalized digital signal;
- and
- a first convolve module configured to convolve the bit stream with a pulse response of the signal processing circuit to generate a first convolved signal;
- a timing module configured to detect a timing error based on the digital signal before being equalized and the first convolved signal, and to adjust the sampling clock signal based on the timing error.
A method, comprising:
- receiving an analog signal;
- sampling and converting, based on a sampling clock signal, the analog signal into a digital signal;
- equalizing the digital signal;
- detecting a bit stream from the equalized digital signal;
- convolving the bit stream with a pulse response to generate a first convolved signal;
- detecting a timing error based on the digital signal before being equalized and the first convolved signal;
- and
- adjusting the sampling clock signal based on the timing error.
An electronic system, comprising:
- a pick-up unit configured to generate an electrical signal corresponding to a bit stream;
- an analog signal processing circuit configured to generate an analog signal based on the electrical signal;
- an analog to digital converter (ADC) configured to sample the analog signal based on a sampling clock signal, and convert the sampled analog signal into a digital signal;
- an equalizer configured to equalize the digital signal;
- a detector configured to detect a bit stream from the equalized digital signal;
- and
- a first convolve module configured to convolve the bit stream with a pulse response of the signal processing circuit to generate a first convolved signal;
- a timing module configured to detect a timing error based on the digital signal before being equalized and the first convolved signal, and to adjust the sampling clock signal based on the timing error.
Dependencies are inferred from the claim text.