Back to results
US 8,576,007 B2Granted
High speed amplifier
AssigneeTexas Instruments Incorporated
InventorsMarco Corsi, Victoria W. Limketkai, Venkatesh Srinivasan
Life of this patent
Estimating the term…
Abstract
For high speed amplifiers, the parasitic capacitances from the differential input pair introduce a zero that can affect performance. Here, a neutralization network has been provided that compensates for this zero by shifting its position. This is generally accomplished by using a pair of capacitors that are cross-coupled across the differential input pair of the amplifier.
Claims10
An apparatus comprising:
- an amplifier that receives an input signal and that generates an output signal, wherein the amplifier includes:
- a first transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the first transistor receives a first portion of the input signal;
- and
- a second transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the second transistor receives a second portion of the input signal;
- and
- a neutralization network having:
- a first neutralization capacitor that is coupled between the control electrode of the first transistor and the second passive electrode of the second transistor;
- and
- a second neutralization capacitor that is coupled between the control electrode of the second transistor and the second passive electrode of the first transistor,
- wherein the amplifier further comprises:
- a first output terminal that is adapted to provide a first portion of the output signal;
- a second output terminal that is adapted to provide a second portion of the output signal;
- a first bias network that is coupled to the first passive electrode of each of the first and second transistors;
- and
- a second bias network that is coupled to the second passive electrode of each of the first and second transistors,
- wherein the first and second transistors are MOS transistors, and wherein the first passive electrode, the second passive electrode, and the control electrode of each of the first and second transistors are the source, drain, and gate, respectively,
- wherein the first and second transistors further comprise first and second PMOS transistors, respectively,
- wherein the first bias network further comprises:
- a third PMOS transistor that is coupled to the source of the first PMOS transistor at its drain;
- and
- a fourth PMOS transistor that is coupled to the source of the second PMOS transistor at is drain and that is coupled to the gate of the third PMOS transistor at its gate.
18 more elements
The apparatus of 1, wherein the second bias network further comprises:
- a fifth PMOS transistor that is coupled to the drain of the first PMOS transistor at its source;
- and
- a sixth PMOS transistor that is coupled to the drain of the second PMOS transistor at is source and that is coupled to the gate of the fifth PMOS transistor at its gate.
An apparatus comprising:
- a amplifier that receives an input signal and that generates an output signal, wherein the amplifier includes:
- a first transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the first transistor receives a first portion of the input signal;
- a second transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the second transistor receives a second portion of the input signal;
- and
- a plurality of bias networks that are coupled to at least one of the first passive electrode and the second passive electrode of each of the first and second transistors;
- and
- a neutralization network having:
- a first neutralization capacitor that is coupled between the control electrode of the first transistor and the second passive electrode of the second transistor;
- and
- a second neutralization capacitor that is coupled between the control electrode of the second transistor and the second passive electrode of the first transistor,
- wherein the first and second transistors are MOS transistors, and wherein the first passive electrode, the second passive electrode, and the control electrode of each of the first and second transistors are the source, drain, and gate, respectively,
- wherein the first and second transistors further comprise first and second PMOS transistors, respectively,
- wherein the plurality of bias networks further comprises a first bias network, and wherein the first bias network further comprises:
- a third PMOS transistor that is coupled to the source of the first PMOS transistor at its drain;
- and
- a fourth PMOS transistor that is coupled to the source of the second PMOS transistor at is drain and that is coupled to the gate of the third PMOS transistor at its gate.
13 more elements
An apparatus comprising:
- a first output terminal;
- a second output terminal;
- a first PMOS transistor;
- a second PMOS transistor that is coupled to the first PMOS transistor at its gate, wherein the first and second PMOS transistors receive a first bias at their gates;
- a third PMOS transistor that is coupled to the drain of the first PMOS transistor at its source and that receives a first portion of a differential input signal at its gate;
- a fourth PMOS transistor that is coupled to the drain of the second PMOS transistor at its source and that receives a second portion of the differential input signal at its gate;
- a fifth PMOS transistor that is coupled to the drain of the third PMOS transistor at its source and the first output terminal at its drain;
- a sixth PMOS transistor that is coupled to the drain of the fourth PMOS transistor at its source, the second output terminal at its drain, and the gate of the fifth PMOS transistor at its gate, wherein the fifth and sixth PMOS transistors receive a second bias at their gates;
- a first NMOS transistor that is coupled to the drain of the fifth PMOS transistor at its drain;
- a second NMOS transistor that is coupled to the drain of the sixth PMOS transistor at its drain and the gate of the first NMOS transistor at its gate, wherein the first and second NMOS transistors receive a third bias at their gates;
- a first neutralization capacitor that is coupled between the gate of the third PMOS transistor and the drain of the fourth PMOS transistor;
- and
- a second neutralization capacitor that is coupled between the gate of the fourth PMOS transistor and the drain of the third PMOS transistor.
10 more elements
Dependencies are inferred from the claim text.