Waveform generation circuit for a waveform generator
AssigneeTektronix, Inc.
InventorRyoichi Sakai
Life of this patent
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Abstract
A waveform generator has a waveform generation circuit storing waveform data for an analog waveform signals having dead time periods without the need for storing data on the dead time. A sequencer having a sequence memory stores sequence data that controls the sequencing of one or more signal components and associated dead times of the analog waveform signal. The timing of the dead time is controlled by a sampling clock and a wait time counter. The generation of the signal components is controlled by the sampling clock controlling the generation of addresses for a waveform memory storing digital data of the sampling components. The waveform memory digital data is converted to an analog waveform signal.
Claims15
A waveform generation circuit for an arbitrary waveform generator comprising:
- a clock generator for generating a sampling clock;
- a waveform memory for storing data of one or more signal components of an output waveform signal;
- a digital to analog converter for converting the data of the signal components from the waveform memory as the output waveform signal;
- a sequencer having a sequence memory for storing sequence control data representing one or more signal components and related dead times;
- an address counter receiving sequence control initial address data of a selected one of the signal components and providing the initial address to the waveform memory;
- a wait counter receiving sequence control wait time data for the dead time of a selected signal component and counting the sampling clock until a terminal count of the wait time data is reached during which the waveform memory outputs data associated with the initial address of the signal component and generating a signal to initiate incremental addresses from the address counter to the waveform memory for the selected signal component data;
- and
- a signal component length counter receiving sequence control signal component length data and the incremental address initiate signal for counting the sampling clock for the duration of the selected signal component and generating a signal representing the end of the selected signal component of the output waveform signal and terminating the generation of addresses from the address counter, wherein the signal representing the end of the selected signal component initiates one of repeating the selected signal component and selecting sequence control data representing another signal component and related dead time.
A method for controlling the sequence of waveform generation used for an arbitrary waveform generator comprising steps of:
- storing waveform data of one of more signal components of an output waveform signal in a waveform memory;
- providing sequence control data on one of the signal components from a sequence memory to an address counter, a wait counter and a signal component length counter;
- counting a sampling clock with the wait counter for a wait time representing a dead time associated with a selected signal component based on a sequence control data wait time while the address counter provides an initial address of the waveform data of the selected signal component to a waveform memory;
- providing a start signal from the wait counter to the address and signal component length counters when a terminal count based on the sequence control data wait time for the wait counter is achieved;
- incrementing addresses from the address counter to the waveform memory in response to the sampling clock after the address counter receives the start signal;
- counting the sampling clock with the signal component length counter representing the signal component length based on sequence control data signal component length after the signal component length counter receives the start signal;
- providing an end signal from the signal component length counter when a terminal count based on the sequence control data signal component length is achieved;
- and
- providing sequence control data from the sequence memory to the address, wait and signal component length counters another one of the signal components in response to the signal component length end signal.
Dependencies are inferred from the claim text.