Systems and methods including features of power supply noise reduction and/or power-saving for high speed delay lines
AssigneeGSI Technology, Inc.
InventorsJae Hyeong Kim, Jyn-Bang Shyu, Lee-Lean Shu
Life of this patent
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Abstract
The present disclosure relates to systems and methods of noise reduction and/or power saving. According to one or more illustrative implementations, for example, innovations consistent with delay lines in clock/timing circuits such as Delay-Lock-Loop (DLL) and/or Duty Cycle Correction (DCC) circuits are disclosed.
Claims21
A clock/phase component comprising:
- DLL/DCC circuitry including a plurality of delay cells;
- and
- circuitry configured to:
- initiate a digital phase locking procedure in the clock/phase circuitry;
- upon activation of a DLL/DCC circuitry for the first time, turn on only a first subgroup (N) of the delay cells;
- wherein power consumption and/or current spikes in the clock/phase circuitry are reduced.
A method of operating delay cells associated with clock/phase circuitry, the method comprising:
- initiating a phase locking procedure in the clock/phase circuitry;
- upon activation of the circuitry for the first time, turning on only a first subgroup (N) of the delay cells;
- and
- turning on an increasing quantity of the remaining delay cells in installments of single cells and/or small subgroups over time until the phase-locking conditions are achieved;
- wherein power consumption and/or current spikes in the clock/phase circuitry are reduced.
A method of powering delay cells to reduce power consumption and/or adverse effects of power on surges in clock/phase circuitry that includes DLL and/or DCC circuitry and a plurality of delay cells, the method comprising:
- initiating a digital phase locking procedure in the clock/phase circuitry;
- upon activation of a DLL/DCC circuitry for the first time, turning on only a first subgroup (N) of the delay cells;
- and
- turning on an increasing quantity of the remaining delay cells in installments of single cells and/or small subgroups over time until the phase-locking conditions of DLL/DCC are achieved;
- wherein power consumption and/or current spikes in the clock/phase circuitry are reduced.
Dependencies are inferred from the claim text.