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US 8,575,980 B2Granted
PLL circuit, error correcting method for the same, and communication apparatus including the same
AssigneeSony Corporation
InventorShinichiro Tsuda
Life of this patent
Estimating the term…
Abstract
A PLL circuit includes: the number-of-accumulated clocks detecting portion detecting the number of accumulated clocks of an oscillation circuit as a digital value; a periodicity detecting portion detecting periodicity of a digital value of a fractional portion of the number of accumulated clocks of the oscillation circuit with a first reference clock as a reference; a corrected value calculating portion calculating a corrected value; and an adding portion adding the corrected value to the fractional portion of the number of accumulated clocks with the first reference clock from the starting points of the periods of the periodicity.
Claims17
A PLL circuit, PLL standing for phase locked loop, comprising:
- a number-of-accumulated clocks detecting portion detecting the number of accumulated clocks of an oscillation circuit as a digital value;
- a periodicity detecting portion detecting periodicity of a digital value of a fractional portion of the number of accumulated clocks of said oscillation circuit with a first reference clock as a reference;
- a corrected value calculating portion calculating a corrected value from a digital value of one period of an output clock of said oscillation circuit, a digital value of one period of periodicity which the fractional portion of the number of accumulated clocks of said oscillator circuit has, and a value obtained by counting the number of first reference clocks from starting points of periods of the periodicity which the fractional portion of the number of accumulated clocks of said oscillator circuit has;
- and
- an adding portion adding the corrected value to the fractional portion of the number of accumulated clocks with the first reference clock from the starting points of the periods of the periodicity.
2 more elements
An error correcting method for a PLL circuit, PLL standing for phase locked loop, comprising:
- detecting the number of accumulated clocks of an oscillation circuit as a digital value;
- detecting periodicity of a digital value of a fractional portion of the number of accumulated clocks of said oscillation circuit with a first reference clock as a reference;
- calculating a corrected value from a digital value of one period of an output clock of said oscillation circuit, a digital value of one period of periodicity which the fractional portion of the number of accumulated clocks of said oscillator circuit has, and a value obtained by counting the number of first reference clocks from starting points of periods of the periodicity which the fractional portion of the number of accumulated clocks of said oscillator circuit has;
- and
- adding the corrected value to the fractional portion of the number of accumulated clocks with the first reference clock from the starting points of the periods of the periodicity.
2 more elements
A communication apparatus, comprising:
- a PLL circuit, PLL standing for phase locked loop, including
- a number-of-accumulated clocks detecting portion detecting the number of accumulated clocks of an oscillation circuit as a digital value,
- a periodicity detecting portion detecting periodicity of a digital value of a fractional portion of the number of accumulated clocks of said oscillation circuit with a first reference clock as a reference,
- a corrected value calculating portion calculating a corrected value from a digital value of one period of an output clock of said oscillation circuit, a digital value of one period of periodicity which the fractional portion of the number of accumulated clocks of said oscillator circuit has, and a value obtained by counting the number of first reference clocks from starting points of periods of the periodicity which the fractional portion of the number of accumulated clocks of said oscillator circuit has, and
- an adding portion adding the corrected value to the fractional portion of the number of accumulated clocks with the first reference clock from the starting points of the periods of the periodicity.
2 more elements
A correction circuitry, comprising:
- a clock output portion outputting a plurality of clocks;
- a first detecting portion detecting a number of accumulated clocks outputted from the clock output portion as a digital value;
- a second detecting portion detecting periodicity of a digital value of a fractional portion of the number of accumulated clocks with a first reference clock as a reference;
- a calculating portion calculating a correction value from
- a digital value of one period of an output clock from said clock output portion,
- a digital value of one period of periodicity which the fractional portion of the number of accumulated clocks has, and
- a value obtained by counting a number of first reference clocks from starting points of periods of the periodicity which the fractional portion of the number of accumulated clocks from said clock output portion has;
- and
- a correcting portion correcting the fractional portion of the number of accumulated clocks with the first reference clock from the starting points of the periods of the periodicity according to the correction value.
6 more elements
Dependencies are inferred from the claim text.