Low voltage supply comparator and a method to operate the comparator

A comparator, comprising:

• a mirror circuit that is coupled to a first voltage source and a second voltage source;
• a first P-type Metal Oxide Semiconductor (PMOS) transistor coupled to the first voltage source and an output terminal of the comparator, wherein the first PMOS transistor is biased by an output of the mirror circuit;
• and
• a first N-type Metal Oxide Semiconductor (NMOS) transistor coupled to a ground terminal and the output terminal of the comparator, wherein the first NMOS transistor is biased by the output of the mirror circuit, and wherein a current level flowing through the first NMOS transistor is substantially equivalent to a current level flowing through the first PMOS transistor;
• wherein the mirror circuit further comprises:
• a second PMOS transistor, wherein a drain of the second PMOS transistor is coupled to a gate of the first PMOS transistor;
• a third PMOS transistor, wherein a gate of the third PMOS transistor is coupled to the gate of the second PMOS transistor and to a drain of the third PMOS transistor;
• a second NMOS transistor, wherein a gate of the second NMOS transistor is coupled to the second voltage source, wherein a drain of the second NMOS transistor is coupled to the drain of the second PMOS transistor;
• a third NMOS transistor, wherein a gate of the third NMOS transistor is coupled to the first voltage source, wherein a drain of the third NMOS transistor is coupled to a drain of the third PMOS transistor;
• a fourth NMOS transistor, wherein a drain of the fourth NMOS transistor is coupled to a source of the second NMOS transistor and a source of the third NMOS transistor;
• a fourth PMOS transistor, wherein a gate of the fourth PMOS transistor is coupled to the drain of the third PMOS transistor and the drain of the third NMOS transistor;
• and
• a fifth NMOS transistor, wherein a drain of the fifth NMOS transistor is coupled to a drain of the fourth PMOS transistor, and wherein a gate of the fifth NMOS transistor is coupled to a gate of the first NMOS transistor and the drain of the fifth NMOS transistor.