US 8,575,973 B1 · Frequency synthesizer with zero deterministic jitter

Abstract

A frequency synthesizer system may generate two intermediate clock signals, each intermediate clock signal having the same nominal frequency (fN), the same cycle pattern with deterministic jitter, and the same corresponding average frequency (fA). However, the cycle pattern in one intermediate clock signal may be a specified number (N) of cycles out of phase with respect to the cycle pattern in the other intermediate clock signal. The cycle pattern may recur every 2N cycles in each intermediate clock signal. The duration of each cycle in each of the two intermediate clock signals is defined by fN and the deterministic jitter in the cycle pattern. An output clock signal may be generated by phase interpolating by two (2) the two intermediate clock signals, and dividing the resulting phase interpolated clock signal by N. The resulting output clock signal has an accurate frequency commensurate with fA/N, and is free of deterministic jitter.

Claims22

Dependent claims

A frequency synthesizer system (FSS) comprising:

a first circuit configured to generate a first periodic signal having a first frequency and a repeating first cycle pattern with deterministic jitter;
a second circuit configured to generate a second periodic signal having the first frequency and the repeating first cycle pattern with deterministic jitter, wherein the repeating first cycle pattern in the second periodic signal is a first number (N) of cycles out of phase with respect to the repeating first cycle pattern in the first periodic signal;
and
a third circuit configured to generate a third periodic signal from the first periodic signal and the second periodic signal, wherein the third periodic signal has a second cycle pattern free of deterministic jitter and repeating every N cycles;
wherein a duration of each cycle of the N cycles is defined by the first frequency and the repeating first cycle pattern;
and
wherein N is a nonzero integer.

4 more elements

Dependencies are inferred from the claim text.

Frequency synthesizer with zero deterministic jitter

Life of this patent

Frequency synthesizer with zero deterministic jitter

Life of this patent

Abstract

Claims22